Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 688

Bit Bit Name
3 PER
2 TEND
Rev. 1.0, 09/01, page 644 of 904
Initial Value R/W
0 R/(W)*
1 R
Description
Parity Error
Indicates that a parity error occurred while
receiving in asynchr onous m ode and the reception
has ended abnormally.
[Setting condition]
•
When a parity error is detected during
reception
I f a par i t y er r or occur s, t he r ecei ve dat a i s
t r ansf er r ed t o R D R but t he R D R F f l ag i s not set .
Al so, subsequent ser i al r ecept i on cannot be
cont i nued w hi l e t he PER f l ag i s set t o 1. I n
cl ocked synchr onous m ode, ser i al t r ansm i ssi on
cannot be cont i nued, ei t her .
[Clearing condition]
•
When 0 is written to PER after reading PER =
1
•
The PER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
•
When the TE bit in SCR is 0 and the ERS bit is
also 0
•
If the ERS bit is 0 and the TDRE bit is 1 after
the specified interval after transmission of 1-
byte data
Timing to set this bit differs according to the
register settings.
GM = 0, BLK = 0: 2.5 etu after transmission
GM = 0, BLK = 1: 1.5 etu after transmission
GM = 1, BLK = 0: 1.0 etu after transmission
GM = 1, BLK = 1: 1.0 etu after transmission