Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 29

Figure 7.16 Example of Block Transfer Mode Setting Procedure ..............................................291
Figure 7.17 Example of DMA Transfer Bus Timing ..................................................................292
Figure 7.18 Example of Short Address Mode Transfer ..............................................................293
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)...........................................294
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) ..........................................295
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)...........................296
Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer .................297
Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer .....298
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer ....................299
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer ........300
Figure 7.26 Example of Single Address Mode Transfer (Byte Read).........................................301
Figure 7.27 Example of Single Address Mode (Word Read) Transfer .......................................301
Figure 7.28 Example of Single Address Mode Transfer (Byte Write)........................................302
Figure 7.29 Example of Single Address Mode Transfer (Word Write) ......................................303
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer .....304
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer ........305
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function ..................306
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function................307
Figure 7.34 Example of Multi-Channel Transfer........................................................................308
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt .....................................................................................................309
Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation .......................310
Figure 7.37 Example of Procedure for Clearing Full Address Mode..........................................311
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt.......................................312
Figure 7.39 DMAC Register Update Timing..............................................................................313
Figure 7.40 Contention between DMAC Register Update and CPU Read .................................313
Figure 7.41 Example in Which Low Level is Not Output at TEND Pin.....................................315
Section 8 EXDMA Controller
Figure 8.1 Block Diagram of EXDMAC ....................................................................................318
Figure 8.2 Example of Timing in Dual Address Mode...............................................................333
Figure 8.3 Data Flow in Single Address Mode...........................................................................334
Figure 8.4 Example of Timing in Single Address Mode ............................................................335
Figure 8.5 Example of Timing in Cycle Steal Mode ..................................................................337
Figure 8.6 Examples of Timing in Burst Mode ..........................................................................338
Figure 8.7 Examples of Timing in Normal Transfer Mode ........................................................339
Figure 8.8 Example of Timing in Block Transfer Mode.............................................................340
Figure 8.9 Example of Repeat Area Function Operation ............................................................341
Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode...................342
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and Block Transfer Mode 344
Figure 8.12 Procedure for Changing Register Settings in Operating Channel............................345
Figure 8.13 Example of Channel Priority Timing.......................................................................347
Figure 8.14 Examples of Channel Priority Timing .....................................................................348
Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer ..........................349
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