Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 533

Bit Bit Name
7 —
to
4
3 PH3DDR
2 PH2DDR
1 PH1DDR
0 PH0DDR
Note: 1. Not used in H8S/2378 series.
2. When SDRAM interface is not used, input a low-level signal on the DCTL pin.
Initial Value R/W
0 —
0 W
0 W
0 W
0 W
Description
Reserved
•
Modes 1, 2, 4, 5, 6, and 7 (when EXPE = 1)
When the 2( output enable bit (OEE) and 2( output select bit
(OES) are set to 1, pin PH3 functions as the 2( output pin.
Otherwise, when bit CS7E is set to 1, pin PH3 functions as a &6
output pin when the corresponding PH3DDR bit is set to 1, and as
an input port when the bit is cleared to 0. When bit CS7E is cleared
to 0, pin PH3 is an I/O port, and its function can be switched with
PH3DDR. When areas 2 to 5 are specified as continuous SDRAM
space*1, 2( output is CKE output.
When bit CS6E is set to 1, setting bit PH2DDR makes pin PH2
function as the &69 output pin and as an I/O port when the bit is
cleared to 0. When bit CS6E is cleared to 0, pin PH2 is an I/O port,
and its function can be switched with PH2DDR.
Pin PH1 functions as the SDRAMφ*
is high. Pin PH1 functions as the &68 output pin
2
of the DCTL pin*
when the input level of the DCTL pin*
normal space, and bit PH1DDR is set to 1; if the bit is cleared to 0,
pin PH1 functions as an I/O port. When bit CS5E is cleared to 0, pin
PH1 is an I/O port, and its function can be switched with PH1DDR.
When area 5 is specified as DRAM space and bit CS5E is set to 1,
pin PH1 functions as the 5$68 output pin and as an I/O port when
the bit is cleared to 0.
Pin PH0 functions as the &67 output pin when area 4 is specified as
normal space and bit PH0DDR is set to 1; if the bit is cleared to 0,
pin PH0 functions as an I/O port. When bit CS4E is cleared to 0, pin
PH0 is an I/O port, and its function can be switched with PH0DDR.
When area 4 is specified as DRAM space and bit CS5E is set to 1,
pin PH0 functions as the 5$67 output pin and as an I/O port when
the bit is cleared to 0. When areas 2 to 5 are specified as continuous
, pin PH0 functions as the :( output pin and as an I/O
1
SDRAM*
port when the bit is cleared to 0.
•
Mode 7 (when EXPE = 0)
Pins PH3 to PH0 are I/O ports, and their functions can be switched
with PHDDR.
Pin PH1 functions as the SDRAMφ output pin when the input level of
the DCTL pin is high. When the input level of the DCTL pin is low,
pin PH1 is an I/O port and its function can be switched with PHDDR.
Rev. 1.0, 09/01, page 489 of 904
1
output pin when the input level
2
is low, area 5 is specified as