Serial Control Register (Scr) - Hitachi H8/3035 Series Hardware Manual

11.2.6 Serial Control Register (SCR)

SCR enables the SCI transmitter and receiver, enables or disables serial clock output in
asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.
Bit 7
TIE
Initial value 0
Read/Write R/W
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TXI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty
interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit
data from TDR to TSR.
Bit 7
TIE Description
0 Transmit-data-empty interrupt request (TXI) is disabled*
1 Transmit-data-empty interrupt request (TXI) is enabled
Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then
clearing it to 0; or by clearing the TIE bit to 0.
6 5 4
RIE TE RE
0 0 0
R/W R/W R/W
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RXI) and
receive-error interrupts (ERI)
3 2 1
MPIE TEIE CKE1
0 0 0
R/W R/W R/W
Clock enable 1/0
These bits select the
SCI clock source
Transmit end interrupt enable
Enables or disables transmit-
end interrupts (TEI)
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
0
CKE0
0
R/W
(Initial value)
297