Timing Of Cmfa And Cmfb Setting When Compare-Match Occurs; Timing Of Timer Output When Compare-Match Occurs - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

ø
External clock
input pin
Clock input
to TCNT
TCNT
13.5.2

Timing of CMFA and CMFB Setting when Compare-Match Occurs

The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT
match, the compare match signal is not generated until the next incrementation clock input.
Figure 13.5 shows this timing.
ø
TCNT
TCOR
Compare match
signal
CMF
13.5.3

Timing of Timer Output when Compare-Match Occurs

When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR.
Figure 13.6 shows the timing when the output is set to toggle at compare match A.
N–1
Figure 13.4 Count Timing for External Clock Input
N
N
Figure 13.5 Timing of CMF Setting
N
N+1
Rev. 1.0, 09/01, page 601 of 904
N+1