Dmac And Exdmac Single Address Transfer Mode And Synchronous Dram Interface - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM
Interface
When burst mode is selected on the synchronous DRAM interface, the '$&. and ('$&. output
timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous
DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits
select whether or not burst access is to be performed. The establishment time for the read data can
be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits.
(1) Output Timing of '$&.
When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,
irrespective of the bus master. With the synchronous DRAM interface, the '$&. or ('$&.
output goes low from the T
Figure 6.60 shows the '$&. or ('$&. output timing for the synchronous DRAM interface
when DDS = 1 or EDDS = 1.
Rev. 1.0, 09/01, page 206 of 904
'$&. or ('$&. ('$&.
'$&. '$&. ('$&. ('$&.
state.
c1