Page 3 The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3937 Series and H8/3937R Series include, a FLEX™ decoder*, five kinds of timers, a 2- channel serial communication interface, and an A/D converter, as on-chip peripheral functions necessary for system configuration.
Page 5: Table Of Contents
Contents Section 1 Overview ......................Overview ..........................Internal Block Diagram ...................... Pin Arrangement and Functions..................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions......................Section 2 ........................13 Overview ..........................13 2.1.1 Features ......................... 13 2.1.2 Address Space....................... 14 2.1.3 Register Configuration ..................14 Register Descriptions ......................
Page 6 Memory Map........................47 Application Notes....................... 50 2.9.1 Notes on Data Access ................... 50 2.9.2 Notes on Bit Manipulation ..................52 2.9.3 Notes on Use of the EEPMOV Instruction ............58 Section 3 Exception Handling ..................59 Overview ..........................59 Reset........................... 59 3.2.1 Overview.......................
Page 7 Standby Mode........................105 5.3.1 Transition to Standby Mode.................. 105 5.3.2 Clearing Standby Mode ..................105 5.3.3 Oscillator Settling Time after Standby Mode is Cleared ........105 5.3.4 Standby Mode Transition and Pin States .............. 106 5.3.5 Notes on External Input Signal Changes before/after Standby Mode ....107 Watch Mode ........................
Page 8 7.1.1 Block Diagram ...................... 131 Section 8 I/O Ports ......................133 Overview ..........................133 Port 1 ..........................135 8.2.1 Overview....................... 135 8.2.2 Register Configuration and Description ............... 135 8.2.3 Pin Functions......................140 8.2.4 Pin States....................... 142 8.2.5 MOS Input Pull-Up....................142 Port 2 [Chip Internal I/O Port] ...................
Page 9 Port 8 ..........................168 8.9.1 Overview....................... 168 8.9.2 Register Configuration and Description ............... 168 8.9.3 Pin Functions......................169 8.9.4 Pin States....................... 169 8.10 Port 9 ..........................170 8.10.1 Overview....................... 170 8.10.2 Register Configuration and Description ............... 170 8.10.3 Pin Functions......................172 8.10.4 Pin States.......................
Page 10 Timer G ..........................215 9.5.1 Overview....................... 215 9.5.2 Register Descriptions .................... 217 9.5.3 Noise Canceler ...................... 221 9.5.4 Operation....................... 223 9.5.5 Application Notes ....................227 9.5.6 Timer G Application Example ................232 Watchdog Timer......................... 233 9.6.1 Overview....................... 233 9.6.2 Register Descriptions .................... 234 9.6.3 Timer Operation ....................
Page 11 11.4 Interrupts ..........................323 11.5 Typical Use ........................323 11.6 Application Notes....................... 327 Section 12 FLEX™ Roaming Decoder II ..............329 12.1 Overview ..........................329 12.1.1 Features ......................... 329 12.1.2 System Block Diagram ..................330 12.1.3 Functional Block Diagram ..................332 12.2 SPI Packets..........................
Page 12 12.6.1 SPI Timing ......................387 12.6.2 Start-up Timing..................... 389 12.6.3 Reset Timing......................390 Section 13 Electrical Characteristics ................391 13.1 Absolute Maximum Ratings....................391 13.2 Electrical Characteristics....................392 13.2.1 Power Supply Voltage and Operating Range ............392 13.2.2 DC Characteristics ....................394 13.2.3 AC Characteristics ....................
Page 13: Overview
FLEX™ system, which require low power consumption. Models in the H8/3937 Series and H8/3937R Series are the H8/3935 and H8/3935R, with on-chip 40-kbyte ROM and 2-kbyte RAM, the H8/3936 and H8/3936R, with on-chip 48-kbyte ROM and 2-kbyte RAM, and the H8/3937 and H8/3937R, with on-chip 60-kbyte ROM and 2-kbyte RAM.
Page 14 Table 1-1 Features Item Description High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed  Max. operating speed: 5 MHz  Add/subtract: 0.4 µs (operating at 5 MHz) ...
Page 15 Item Description Memory Large on-chip memory • H8/3935, H8/3935R: 40-kbyte ROM, 2-kbyte RAM • H8/3936, H8/3936R: 48-kbyte ROM, 2-kbyte RAM • H8/3937, H8/3937R: 60-kbyte ROM, 2-kbyte RAM I/O ports 67 pins • 59 I/O pins • 8 input pins • 5 internal I/O •...
Page 16 Item Description A/D converter Successive approximations using a resistance ladder • 8-channel analog input pins • Conversion time: 31/ø or 62/ø per channel FLEX™ On-chip FLEX™ decoder II decoder II • Conforms to FLEX™ protocol revision 1.9 • Decoding capability: 1600, 3200, 6400 bits/second •...
Page 17: Internal Block Diagram
Internal Block Diagram Figure 1-1 shows a block diagram of the H8/3937 Series and H8/3937R Series. TEST20 /TMOW TEST21 /TMOFL TEST22 H8/300L /TMOFH TEST23 /TMIG TEST24 /IRQ /ADTRG TEST43 /IRQ /TMIC /IRQ /IRQ /TMIF (60 k, 48 k, 40 k)
Page 18: Pin Arrangement And Functions
Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3937 Series and H8/3937R Series pin arrangement is shown in figure 1-2. S0/IFIN CLKOUT TESTD P57/WKP7 P56/WKP6 TEST P55/WKP5 P54/WKP4 Top View P53/WKP3 (TFP-100B, TFP-100G) P52/WKP2 P51/WKP1 P50/WKP0 TESTA9H P35/TXD31 P34/RXD31 P33/SCK31...
Page 19: Pin Functions
1.3.2 Pin Functions Table 1-2 outlines the pin functions of the H8/3937 Series and H8/3937R Series. Table 1-2 Pin Functions Pin No. TFP-100B Type Symbol TFP-100G Name and Functions Power Input Power supply: All V pins should be source pins connected to the system power supply.
Page 20 Pin No. TFP-100B Type Symbol TFP-100G Name and Functions Interrupt Input IRQ interrupt request 0 and 1: These are pins input pins for edge-sensitive external interrupts, with a selection of rising or falling edge. 42 to 35 Input Wakeup interrupt request 0 to 7: These are input pins for rising or falling- edge- sensitive external interrupts.
Page 21 Pin No. TFP-100B Type Symbol TFP-100G Name and Functions I/O ports to PA 25 to 22 Port A: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA). to P1 21 to 14 Port 1: This is an 8-bit I/O port.
Page 22 Pin No. TFP-100B Type Symbol TFP-100G Name and Functions Serial Input SCI32 receive data input: This is the communi- SCI32 data input pin. cation Output SCI32 transmit data output: This is the interface SCI32 data output pin. (SCI) SCI32 clock I/O: This is the SCI32 clock I/O pin.
Page 23 Pin No. TFP-100B Type Symbol TFP-100G Name and Functions FLEX™ CLKOUT Output Clock output: 38.4 kHz or 40 kHz clock decoder II output (derived from on-chip crystal oscillator). SYMCLK Output Symbol clock output: Recovered symbol clock pin. Output Receiver control output: Receiver control signal output pin (when using external demodulator).
Page 25: Cpu
Section 2 CPU Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. •...
Page 26: Address Space
2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
Page 27: Register Descriptions
Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
Page 28: Initial Register Values
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see section 3.3, Interrupts. Bit 6—User Bit (U): Can be used freely by the user.
Page 29: Data Formats
Data Formats The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). •...
Page 30: Data Formats In General Registers
2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. Data Format 1-bit data don’t care 1-bit data don’t care Byte data don’t care Byte data don’t care Word data...
Page 31: Memory Data Formats
2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed.
Page 32: Addressing Modes
Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes Address Modes Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment @Rn+...
Page 33 The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. •...
Page 34: Effective Address Calculation
If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See 2.3.2, Memory Data Formats, for further information. 2.4.2 Effective Address Calculation Table 2-2 shows how effective addresses are calculated in each of the addressing modes.
Page 35 Table 2-2 Effective Address Calculation...
Page 38: Instruction Set
Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Instructions Number Data transfer MOV, PUSH* , POP* Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, OR, XOR, NOT...
Page 39 Notation General register (destination) General register (source) General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer #IMM...
Page 40: Data Transfer Instructions
2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Page 41 Rm→Rn @Rm←→Rn @(d:16, Rm)←→Rn disp @Rm+→Rn, or Rn →@–Rm @aa:8←→Rn @aa:16←→Rn #xx:8→Rn #xx:16→Rn PUSH, POP → @SP+ Rn, or → @–SP Notation: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-5 Data Transfer Instruction Codes...
Page 42: Arithmetic Operations
2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.
Page 43: Logic Operations
2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data Rd ∨...
Page 44 Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#XX:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Notation:...
Page 45: Bit Manipulations
2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <Ead>) BSET Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 46 Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. C ⊕ [~(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
Page 47 BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Operand:...
Page 48 BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Notation: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont)
Page 49: Branching Instructions
2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Size Function — Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition...
Page 50 disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) Notation: Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2-8 Branching Instruction Codes...
Page 51: System Control Instructions
2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Instruction Size* Function — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details.
Page 52: Block Data Transfer Instruction
RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) Notation: Operation field Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction Instruction Size...
Page 53 Notation: Operation field Figure 2-10 Block Data Transfer Instruction Code...
Page 54: Basic Operational Timing
Basic Operational Timing CPU operation is synchronized by a system clock (ø) or a subclock (ø ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
Page 55: Access To On-Chip Peripheral Modules
2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Page 56 Three-state access to on-chip peripheral modules Bus cycle state state state ø or ø Internal Address address bus Internal read signal Internal Read data data bus (read access) Internal write signal Internal data bus Write data (write access) Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access)
Page 57: Cpu States
CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode.
Page 58: Program Execution State
Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs occurs source handling occurs complete Program halt state Program execution state SLEEP instruction executed Figure 2-15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode.
Page 59: Memory Map
Memory Map The memory map of the H8/3935 and H8/3935R is shown in figure 2-16 (1), that of the H8/3936 and H8/3936R in figure 2-16 (2), and that of the H8/3937 and H8/3937R in figure 2-16 (3). H'0000 Interrupt vector area H'0029 H'002A 40 kbytes...
Page 60 H'0000 Interrupt vector area H'0029 H'002A 48 kbytes (49152 bytes) On-chip ROM H'BFFF Not used H'F780 2048 bytes On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2-16 (2) H8/3936 and H8/3936R Memory Map...
Page 61 H'0000 Interrupt vector area H'0029 H'002A 60 kbytes On-chip ROM (60928 bytes) H'EDFF Not used H'F780 2048 bytes On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2-16 (3) H8/3937 and H8/3937R Memory Map...
Page 62: Application Notes
Application Notes 2.9.1 Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
Page 63 Access States Word Byte H'0000 Interrupt vector area (42 bytes) H'0029 H'002A 40 kbytes* On-chip ROM H'9FFF Not used — — — H'F780 On-chip RAM 2048 bytes H'FF7F Not used — — — × H'FF90 × H'FF98 to H'FF9F Internal I/O registers ×...
Page 64: Notes On Bit Manipulation
2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an I/O port.
Page 65 Example 2: BSET instruction executed designating port 3 and P3 are designated as input pins, with a low-level signal input at P3 and a high-level signal at P3 . The remaining pins, P3 to P3 , are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P3 to high-level output.
Page 66 To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] The PDR3 value (H'80) is written to a work area in MOV.
Page 67 2. Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P3 and P3 are input pins, with a low-level signal input at P3 and a high-level signal at P3 .
Page 68 To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] The PCR3 value (H'3F) is written to a work area in MOV.
Page 69 Table 2-12 lists the pairs of registers that share identical addresses. Table 2-13 lists the registers that contain write-only bits. Table 2-12 Registers with Shared Addresses Register Name Abbreviation Address Timer counter and timer load register C TCC/TLC H'FFB5 Port data register 1* PDR1 H'FFD4 Port data register 2*...
Page 70: Notes On Use Of The Eepmov Instruction
2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 → ←...
Page 71: Exception Handling
Section 3 Exception Handling Overview Exception handling is performed in the H8/3937 Series and H8/3937R Series when a reset or interrupt occurs. Table 3-1 shows the priorities of these two types of exception handling. Table 3-1 Exception Handling Types and Priorities...
Page 72: Interrupt Immediately After Reset
When system power is turned on or off, the RES pin should be held low. Figure 3-1 shows the reset sequence starting from RES input. Reset cleared Program initial instruction prefetch Vector fetch Internal processing ø Internal address bus Internal read signal Internal write signal...
Page 73: Interrupts
Interrupts 3.3.1 Overview The interrupt sources that initiate interrupt exception handling comprise 12 external interrupts (WKP to WKP , IRQ to IRQ ), 23 internal interrupts from on-chip peripheral modules, and one internal IRQ interrupt. Table 3-2 shows the interrupt sources, their priorities, and their vector addresses.
Page 74 Table 3-2 Interrupt Sources and Their Priorities Interrupt Source Interrupt Vector Number Vector Address Priority Reset H'0000 to H'0001 High H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 SCI1 SCI1 transfer complete H'0014 to H'0015 Timer A Timer A overflow...
Page 75: Interrupt Control Registers
3.3.2 Interrupt Control Registers Table 3-3 lists the registers that control interrupts. Table 3-3 Interrupt Control Registers Name Abbreviation Initial Value Address IRQ edge select register IEGR H'E0 H'FFF2 Interrupt enable register 1 IENR1 H'00 H'FFF3 Interrupt enable register 2 IENR2 H'00 H'FFF4...
Page 76 Bit 3: IRQ edge select (IEG3) Bit 3 selects the input sensing of the IRQ pin and TMIF pin. Bit 3 IEG3 Description Falling edge of IRQ and TMIF pin input is detected (initial value) Rising edge of IRQ and TMIF pin input is detected Bit 2: IRQ edge select (IEG2) Bit 2 selects the input sensing of pin IRQ...
Page 77 2. Interrupt enable register 1 (IENR1) IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Timer A interrupt enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests. Bit 7 IENTA Description...
Page 78 Bits 4 to 0: IRQ to IRQ interrupt enable (IEN4 to IEN0) Bits 4 to 0 enable or disable IRQ to IRQ interrupt requests. Bit n IENn Description Disables interrupt requests from pin IRQn (initial value) Enables interrupt requests from pin IRQn (n = 4 to 0) Note: IRQ is an internal signal that performs interfacing to the FLEX™...
Page 79 Bit 4: Timer G interrupt enable (IENTG) Bit 4 enables or disables timer G input capture or overflow interrupt requests. Bit 4 IENTG Description Disables timer G interrupt requests (initial value) Enables timer G interrupt requests Bit 3: Timer FH interrupt enable (IENTFH) Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Page 80 4. Interrupt request register 1 (IRR1) IRRTA IRRS1 — IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write — Note: * Only a write of 0 for flag clearing is possible IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A, SCI1, or IRQ to IRQ...
Page 81 Bits 4 to 0: IRQ to IRQ interrupt request flags (IRRI4 to IRRI0) Bit n IRRIn Description Clearing conditions: (initial value) When IRRIn = 1, it is cleared by writing 0 Setting conditions: When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 4 to 0) Note: IRQ...
Page 82 Bit 6: A/D converter interrupt request flag (IRRAD) Bit 6 IRRAD Description Clearing conditions: (initial value) When IRRAD = 1, it is cleared by writing 0 Setting conditions: When A/D conversion is completed and ADSF is cleared to 0 in ADSR Bit 5: Reserved bit Bit 5 is a readable/writable reserved bit.
Page 83 Bit 1: Timer C interrupt request flag (IRRTC) Bit 1 IRRTC Description Clearing conditions: (initial value) When IRRTC= 1, it is cleared by writing 0 Setting conditions: When the timer C counter value overflows (from H'FF to H'00) or underflows (from H'00 to H'FF) Bit 0: Reserved bit Bit 0 is reserved: it is always read as 0 and cannot be modified.
Page 84: External Interrupts
7. Wakeup Edge Select Register (WEGR) WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value Read/Write WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn. WEGR is initialized to H'00 by a reset. Bit n: WKPn edge select (WKEGSn) Bit n selects WKPn pin input sensing.
Page 85: Internal Interrupts
When these pins are designated as pins IRQ to IRQ in port mode register 3 and 1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits IEN4 to IEN1 to 0 in IENR1.
Page 86: 3.3.5 Interrupt Operations
3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the interrupt controller. Figure 3-3 shows the flow up to interrupt acceptance. Interrupt controller External or internal interrupts Interrupt request External interrupts or internal interrupt enable...
Page 87 • If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling.
Page 88 Program execution state IRRI0 = 1 IEN0 = 1 IRRI1 = 1 IEN1 = 1 IRRI2 = 1 IEN2 = 1 IRRDT = 1 IENDT = 1 I = 0 PC contents saved CCR contents saved I ← 1 Branch to interrupt handling routine Notation: Program counter...
Page 89 SP – 4 SP (R7) SP – 3 SP + 1 SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling exception handling...
Page 90 Figure 3-5 Interrupt Sequence...
Page 91: Interrupt Response Time
3.3.6 Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3-4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 13 15 to 27 Saving of PC and CCR to stack...
Page 92: Application Notes
Notes on Stack Area Use When word data is accessed in the H8/3937 Series and H8/3937R Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address.
Page 93: Notes On Rewriting Port Mode Registers
3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ to IRQ , WKP...
Page 94 Table 3-5 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 Conditions When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ IRR1 IRRI4 is low and IEGR bit IEG4 = 0. When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ is low and IEGR bit IEG4 = 1.
Page 95: Notes On Interrupt Request Flag Clearing Methods
Interrupts masked. (Another possibility ← is to disable the relevant interrupt in CCR I bit interrupt enable register 1.) Set port mode register bit After setting the port mode register bit, first execute at least one instruction Execute NOP instruction (e.g., NOP), then clear the interrupt request flag to 0 Clear interrupt request flag to 0...
Page 97: Clock Pulse Generators
Section 4 Clock Pulse Generators Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 98: System Clock Generator
System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. Connecting a crystal oscillator Figure 4-2 shows a typical method of connecting a crystal oscillator. R = 1 MΩ...
Page 99 2. Connecting a ceramic oscillator Figure 4-4 shows a typical method of connecting a ceramic oscillator. R = 1 MΩ ±20% Oscillation Recommended value frequency Manufacturer for C and C 30 pF ±10% 4.0 MHz Murata Seisakusho Figure 4-4 Typical Connection to Ceramic Oscillator 3.
Page 100 4. External clock input method Connect an external clock signal to pin OSC , and leave pin OSC open. Figure 4-6 shows a typical connection. External clock input Open Figure 4-6 External Clock Input (Example) Frequency Oscillator Clock (ø Duty cycle 45% to 55% Caution When a crystal or ceramic oscillator element is connected, circuit constants will differ according...
Page 101: Subclock Generator
Subclock Generator 1. Connecting a 76.8-kHz/160-kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 76.8-kHz/160-kHz crystal oscillator, as shown in figure 4-7. Follow the same precautions as noted under 3. notes on board design for the system clock in 4.2. C = C = 12.5 pF (typ.) Figure 4-7 Typical Connection to 76.8-kHz/160-kHz Crystal Oscillator (Subclock)
Page 102 3. External clock input Connect the external clock to the DX pin and leave the DX pin open, as shown in figure 4-10. External clock input Open Figure 4-10 Pin Connection when Inputting External Clock Frequency Subclock (øw) Duty 45% to 55%...
Page 103: Prescalers
Prescalers The H8/3937 Series and 3937R Series are equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Page 104: Note On Oscillators
Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTAT™ versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors.
Page 105 Oscillation waveform (OSC2) System clock (ø) Oscillation settling time Standby time Standby mode, Operating Active (high-speed) mode or watch mode, Oscillation settling standby time mode active (medium-speed) mode or subactive mode Interrupt accepted Figure 4-11 Oscillation Settling Standby Time When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to change at the point at which the interrupt is accepted.
Page 106: Notes On Use Of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding on the oscillation settling standby time.
Page 107: Power-Down Modes
Section 5 Power-Down Modes Overview The H8/3937 Series and H8/3937R Series have nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5-1 gives a summary of the eight operating modes.
Page 108 Program Program Reset state execution state halt state SLEEP instruction Active Sleep (high-speed) (high-speed) Program mode mode halt state Standby mode SLEEP instruction Active Sleep (medium-speed) (medium-speed) mode mode SLEEP SLEEP instruction instruction Watch Subactive Subsleep mode mode mode Power-down modes Mode Transition Conditions (1) Mode Transition Conditions (2) LSON MSON SSBY...
Page 109 Table 5-2 Internal State in Each Operating Mode Active Mode Sleep Mode High- Medium- High- Medium- Watch Subactive Subsleep Standby Function Speed Speed Speed Speed Mode Mode Mode Mode System clock oscillator Functions Functions Functions Functions Halted Halted Halted Halted Subclock oscillator Functions Functions...
Page 110: System Control Registers
5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5-3. Table 5-3 System Control Registers Name Abbreviation Initial Value Address System control register 1 SYSCR1 H'07 H'FFF0 System control register 2 SYSCR2 H'F0 H'FFF1 1.
Page 111 Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation settling time.
Page 112 Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0) Bits 1 and 0 choose ø /128, ø /64, ø /32, or ø /16 as the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-speed) mode or subactive mode.
Page 113 Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits.
Page 114 Bits 1 and 0: Subactive mode clock select (SA1, SA0) These bits select the CPU clock rate (ø /2, ø /4, or ø /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1 Bit 0 Description ø...
Page 115: Sleep Mode
Sleep Mode 5.2.1 Transition to Sleep Mode 1. Transition to sleep (high-speed) mode The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON bits in SYSCR2 are also cleared to 0.
Page 116: Clock Frequency In Sleep (Medium-Speed) Mode
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1.
Page 117: Standby Mode
Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0.
Page 118: Standby Mode Transition And Pin States
Table 5-4 Clock Frequency and Settling Time (times are in ms) STS2 STS1 STS0 Waiting Time 5 MHz 2 MHz 1 MHz 8,192 states 1.6384 4.096 8.192 16,384 states 3.2768 8.192 16.384 1,024 states 0.2048 0.512 1.024 2,048 states 0.4096 1.024 2.048 4,096 states...
Page 119: Notes On External Input Signal Changes Before/After Standby Mode
5.3.5 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ or WKP is input, both the high- and low-level widths of the signal must be at least two cycles of system clock ø or subclock ø (referred to together in this section as the internal clock).
Page 120 Active (high-speed, Wait for Active (high-speed, Operating medium-speed) mode Standby mode oscillation medium-speed) mode mode or subactive mode or watch mode to settle or subactive mode subcyc subcyc subcyc subcyc ø or ø External input signal Capture possible: case 1 Capture possible: case 2 Capture possible:...
Page 121: Watch Mode
Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F, timer G, and the FLEX™...
Page 122: Subsleep Mode
Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1.
Page 123: Subactive Mode
Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ , or WKP WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer F, timer G, SCI1, SCI31, SCI32, IRQ , or WKP to WKP...
Page 124: Active (Medium-Speed) Mode
Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ , IRQ or WKP...
Page 125: Direct Transfer
Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1.
Page 126: Direct Transition Times
• Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
Page 127 Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal processing states) } × (t before transition) + (number of interrupt exception handling execution states) × (t after transition) ........(2) Example: Direct transition time = (2 + 1) × 16t + 14 ×...
Page 128: Notes On External Input Signal Changes Before/After Direct Transition
4. Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA.
Page 129: Module Standby Mode
Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. This state is identical to standby mode.
Page 130 Table 5-5 Setting and Clearing Module Standby Mode by Clock Stop Register Register Name Bit Name Operation CKSTPR1 TACKSTP Timer A module standby mode is cleared Timer A is set to module standby mode TCCKSTP Timer C module standby mode is cleared Timer C is set to module standby mode TFCKSTP Timer F module standby mode is cleared...
Page 131: Rom
Section 6 ROM Overview The H8/3935 and H8/3935R have 40 kbytes of mask ROM, the H8/3936 and H8/3936R have 48 kbytes of mask ROM, and the H8/3937 and H8/3937R have 60 kbytes of mask ROM on-chip. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data.
Page 132: Prom Mode
PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. However, page programming is not supported. Table 6-1 shows how to set the chip to PROM mode.
Page 133 H8/3937, H8/3937R EPROM socket HN27C101 TFP-100B, TFP-100G (32-pin) TESTA9H 12, 52 TEST 11, 51 TESTD EXS0 EXS1 LOBAT Note: Pins not indicated in the figure should be left open. Figure 6-2 Socket Adapter Pin Correspondence (with HN27C101)
Page 134 Address in Address in MCU mode PROM mode H'0000 H'0000 On-chip PROM H'EDFF H'EDFF Uninstalled area* H'1FFFF Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF.
Page 135: Programming
Programming The write, verify, and other modes are selected as shown in table 6-3 in PROM mode. Table 6-3 Mode Selection in PROM Mode (H8/3937, H8/3937R) Pins Mode to EO to EA Write Data input Address input Verify Data output Address input Programming High i m pedanc e...
Page 136 Start Set write/verify mode = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V Address = 0 n = 0 → n + 1 < = 0.2 ms ± 5% n 25 Write time t No Go →...
Page 137 Table 6-4 and table 6-5 give the electrical characteristics in programming mode. Table 6-4 DC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Test Condi t i on Input high- to EO...
Page 138 Table 6-5 AC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C) Item Symbol Unit Test Condition Address setup time — — µs Figure 6-5* OE setup time — — µs Data setup time —...
Page 139 Figure 6-5 shows a PROM write/verify timing diagram. Write Verify Address Data Input data Output data CC +1 Note: * t is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart. Figure 6-5 PROM Write/Verify Timing...
Page 140: Programming Precautions
) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in correct V of 12.5 V.
Page 141: Reliability Of Programmed Data
If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 143: Ram
Section 7 RAM Overview The H8/3937 Series and H8/3937R Series have 2 kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
Page 145: I/O Ports
Section 8 I/O Ports Overview The H8/3937 Series and H8/3937R Series are provided with six 8-bit I/O ports, two 4-bit I/O ports, one 3-bit I/O port, and one 8-bit input-only port. Also provided are one internal 5-bit I/O port and one internal 1-bit input-only port capable of interfacing to the on-chip FLEX™ decoder.
Page 146 Function Pins and Switching Port Description Functions Other Functions Registers • Port 3 8-bit I/O port SCI31 data output (TXD PMR3 • data input (RXD ), clock SCR31 MOS input pull-up option /TXD input/output (SCK SMR31 /RXD /SCK /RESO Reset output, timer C count- PMR3 up/down select input •...
Page 147: Port 1
Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Figure 8-1 shows its pin configuration. P1 /IRQ /TMIF P1 /IRQ P1 /IRQ /TMIC P1 /IRQ /ADTRG Port 1 P1 /TMIG P1 /TMOFH P1 /TMOFL P1 /TMOW Figure 8-1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8-2 shows the port 1 register configuration.
Page 148 1. Port data register 1 (PDR1) Initial value Read/Write PDR1 is an 8-bit register that stores data for port 1 pins P1 to P1 . If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Page 149 4. Port mode register 1 (PMR1) IRQ3 IRQ2 IRQ1 IRQ4 TMIG TMOFH TMOFL TMOW Initial value Read/Write PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. Bit 7: P1 /IRQ /TMIF pin function switch (IRQ3)
Page 150 Bit 4: P1 /IRQ /ADTRG pin function switch (IRQ4) or as IRQ This bit selects whether pin P1 /IRQ /ADTRG is used as P1 /ADTRG. Bit 4 IRQ4 Description Functions as P1 I/O pin (initial value) Functions as IRQ /ADTRG input pin Note: For details of ADTRG pin setting, see 12.3.2, Start of A/D Conversion by External Trigger.
Page 151 Bit 0: P1 /TMOW pin function switch (TMOW) This bit selects whether pin P1 /TMOW is used as P10 or as TMOW. Bit 0 TMOW Description Functions as P1 I/O pin (initial value) Functions as TMOW output pin...
Page 152: Pin Functions
8.2.3 Pin Functions Table 8-3 shows the port 1 pin functions. Table 8-3 Port 1 Pin Functions Pin Functions and Selection Method /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR1 in PCR1.
Page 153 Pin Functions and Selection Method /TMIG The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1. TMIG PCR1 Pin function input pin output pin TMIG input pin /TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR1 in PCR1.
Page 154: Pin States
8.2.4 Pin States Table 8-4 shows the port 1 pin states in each operating mode. Table 8-4 Port 1 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ /TMIF High- Retains Retains High- Retains Functional Functional /IRQ impedance previous previous impedance*...
Page 155: Port 2 [Chip Internal I/O Port]
Port 2 [Chip Internal I/O Port] 8.3.1 Overview Port 2 is a 5-bit I/O internal port. Figure 8-2 shows its functional configuration. Port 2 is an internal function that performs interfacing to the FLEX™ decoder incorporated in the chip. It cannot be connected to an IC outside the chip. RESET FLEX™...
Page 156 1. Port data register 2 (PDR2) — — — Initial value Read/Write — — — PDR2 is an 8-bit register that stores data for port 2 pins P2 to P2 . If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read directly. Do not read port 2 while PCR2 bits are cleared to 0.
Page 157 Bits 7, 6, 4, and 3: Reserved bits Bits 7, 6, 4, and 3 are reserved; they are always read as 1 and cannot be modified. Bit 5: P2 pin PMOS control (POF1) This bit controls the on/off state of the P2 pin PMOS.
Page 158 4. Port mode register 4 (PMR4) — — — NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 Initial value Read/Write — — — PMR4 is an 8-bit read/write register that controls whether individual port 2 pins are set as CMOS or NMOS open-drain when 1 is set in PCR. A 0 setting should be used for this function.
Page 159: Function
8.3.3 Function Table 8-6 shows the port 2 functions. Table 8-6 Port 2 Functions Functions Functions and Selection Method , P2 The function depends on the corresponding bit in PCR2. (n = 4 or 3) PCR2 Function input output The function depends on bit SO1 in PMR2 and bit PCR2 in PCR2.
Page 160: Port 3
Port 3 8.4.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8-3. P3 /TXD P3 /RXD Port 3 P3 /SCK P3 /RESO P3 /UD Figure 8-3 Port 3 Pin Configuration 8.4.2 Register Configuration and Description Table 8-8 shows the port 3 register configuration.
Page 161 1. Port data register 3 (PDR3) Initial value Read/Write PDR3 is an 8-bit register that stores data for port 3 pins P3 to P3 . If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
Page 162 4. Port mode register 3 (PMR3) — — WDCKS IRQ0 RESO — Initial value Read/Write — — — PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'04. Bits 7, 6, and 0: Reserved bits These bits are reserved: they are always read as 0 and cannot be modified.
Page 163: Pin Functions
Bit 2: P3 /RESO pin function switch (RESO) or as RESO. This bit selects whether pin P3 /RESO is used as P3 Bit 2 RESO Description Functions as P3 I/O pin Functions as RESO output pin (initial value) Bit 1: P3 /UD pin function switch (UD) This bit selects whether pin P3 /UD is used as P3...
Page 164 Pin Functions and Selection Method /SCK The pin function depends on bits CKE1, CKE0, and SMR31 in SCR31 and bit PCR3 in PCR3. CKE1 CKE0 COM3 PCR3 Pin function input pin P3 output pin output pin input pin /RESO The pin function depends on bit RESO in PMR3 and bit PCR3 in PCR3.
Page 165: Pin States
8.4.4 Pin States Table 8-10 shows the port 3 pin states in each operating mode. Table 8-10 Port 3 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active High- Retains Retains High- Retains Functional Functional impedance previous previous impedance* previous /TXD state...
Page 166: Port 4
Port 4* Note: * P4 /IRQ , only, is a chip internal input port. 8.5.1 Overview Port 4 is a 3-bit I/O port and 1-bit input internal port, configured as shown in figure 8-4. P4 /IRQ is an internal function that performs interfacing to the FLEX™ decoder incorporated in the chip. It cannot be connected to an IC outside the chip.
Page 167 1. Port data register 4 (PDR4) — — — — Initial value Read/Write — — — — PDR4 is an 8-bit register that stores data for port 4 pins P4 to P4 . If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states.
Page 168: Pin Functions
8.5.3 Pin Functions Table 8-12 shows the port 4 pin functions. Table 8-12 Port 4 Pin Functions Pin Functions and Selection Method /IRQ The function depends on bit IRQ0 in PMR3. IRQ0 Function input input /TXD The pin function depends on bit TE in SCR32, bit SPC32 in SPCR, and bit PCR4 in PCR4.
Page 169: Pin States
8.5.4 Pin States Table 8-13 shows the port 4 pin states in each operating mode. Table 8-13 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ High Retains Retains Retains Retains Functional Functional previous previous previous previous state state...
Page 170: Port 5
Port 5 8.6.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8-5. /WKP /WKP /WKP /WKP Port 5 /WKP /WKP /WKP /WKP Figure 8-5 Port 5 Pin Configuration 8.6.2 Register Configuration and Description Table 8-14 shows the port 5 register configuration. Table 8-14 Port 5 Registers Name Abbrev.
Page 171 1. Port data register 5 (PDR5) Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P5 to P5 . If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Page 172: Pin Functions
4. Port mode register 5 (PMR5) Initial value Read/Write PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n: P5 /WKP pin function switch (WKP or WKP These bits select whether the pin is used as P5 Bit n...
Page 173: Pin States
8.6.4 Pin States Table 8-16 shows the port 5 pin states in each operating mode. Table 8-16 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /WKP High- Retains Retains High- Retains Functional Functional / WKP impedance previous previous impedance*...
Page 174: Port 6
Port 6 8.7.1 Overview Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8-6. Port 6 Figure 8-6 Port 6 Pin Configuration 8.7.2 Register Configuration and Description Table 8-17 shows the port 6 register configuration. Table 8-17 Port 6 Registers Name Abbrev.
Page 175 1. Port data register 6 (PDR6) Initial value Read/Write PDR6 is an 8-bit register that stores data for port 6 pins P6 to P6 If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states.
Page 176: Pin Functions
8.7.3 Pin Functions Table 8-18 shows the port 6 pin functions. Table 8-18 Port 6 Pin Functions Pin Functions and Selection Method to P6 The pin function depends on bit PCR6 in PCR6. (n = 7 to 0) PCR6 Pin function input pin output pin 8.7.4...
Page 177: Port 7
Port 7 8.8.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8-7. Port 7 Figure 8-7 Port 7 Pin Configuration 8.8.2 Register Configuration and Description Table 8-20 shows the port 7 register configuration. Table 8-20 Port 7 Registers Name Abbrev.
Page 178 1. Port data register 7 (PDR7) Initial value Read/Write PDR7 is an 8-bit register that stores data for port 7 pins P7 to P7 . If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
Page 179: Pin Functions
8.8.3 Pin Functions Table 8-21 shows the port 7 pin functions. Table 8-21 Port 7 Pin Functions Pin Functions and Selection Method to P7 The pin function depends on bit PCR7 in PCR7. (n = 7 to 0) PCR7 Pin function input pin output pin 8.8.4...
Page 180: Port 8
Port 8 8.9.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8-8. Port 8 Figure 8-8 Port 8 Pin Configuration 8.9.2 Register Configuration and Description Table 8-23 shows the port 8 register configuration. Table 8-23 Port 8 Registers Name Abbrev.
Page 181: Pin Functions
2. Port control register 8 (PCR8) PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 Initial value Read/Write PCR8 is an 8-bit register for controlling whether each of the port 8 pins P8 to P8 functions as an input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 182: Port 9
8.10 Port 9 8.10.1 Overview Port 9 is a 4-bit I/O port. Figure 8-9 shows its pin configuration. Port 9 Figure 8-9 Port 9 Pin Configuration 8.10.2 Register Configuration and Description Table 8-26 shows the port 9 register configuration. Table 8-26 Port 9 Registers Name Abbrev.
Page 183 1. Port data register 9 (PDR9) — — — — Initial value Read/Write — — — — PDR9 is an 8-bit register that stores data for port 9 pins P9 to P9 . If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states.
Page 184: Pin Functions
8.10.3 Pin Functions Table 8-27 shows the port 9 pin functions. Table 8-27 Port 9 Pin Functions Pin Functions and Selection Method to P9 The pin function depends on bit PCR9 in PCR9. (n = 3 to 0) PCR9 Pin function input pin output pin 8.10.4...
Page 185: Port A
8.11 Port A 8.11.1 Overview Port A is a 4-bit I/O port, configured as shown in figure 8-10. Port A Figure 8-10 Port A Pin Configuration 8.11.2 Register Configuration and Description Table 8-29 shows the port A register configuration. Table 8-29 Port A Registers Name Abbrev.
Page 186: Pin States
2. Port control register A (PCRA) — — — — PCRA PCRA PCRA PCRA Initial value Read/Write — — — — PCRA controls whether each of port A pins PA to PA functions as an input pin or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 187: Port B
8.12 Port B 8.12.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8-11. Port B Figure 8-11 Port B Pin Configuration 8.12.2 Register Configuration and Description Table 8-32 shows the port B register configuration. Table 8-32 Port B Register Name Abbrev.
Page 188: Input/Output Data Inversion Function
8.13 Input/Output Data Inversion Function 8.13.1 Overview With input pins RXD , and RXD , and output pins TXD and TXD , the data can be handled in inverted form. SCINV0 SCINV2 /RXD /RXD SCINV1 SCINV3 /TXD /TXD Figure 8.12 Input/Output Data Inversion Function 8.13.2 Register Configuration and Descriptions Table 8.33 shows the registers used by the input/output data inversion function.
Page 189 Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. Bit 5: P4 /TXD pin function switch (SPC32) This bit selects whether pin P4 /TXD is used as P4 or as TXD Bit 5 SPC32...
Page 190: Note On Modification Of Serial Port Control Register
Bit 1: TXD pin output data inversion switch Bit 1 specifies whether or not TXD pin output data is to be inverted. Bit 1 SCINV1 Description output data is not inverted (initial value) output data is inverted Bit 0: RXD pin input data inversion switch Bit 0 specifies whether or not RXD pin input data is to be inverted.
Page 191: Timers
Section 9 Timers Overview The H8/3937 Series and H8/3937R Series provide five timers: timers A, C, F, G, and a watchdog timer. The functions of these timers are outlined in table 9-1. Table 9-1 Timer Functions Event Waveform Name Functions...
Page 192: Timer A
Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and time-base functions. A clock signal divided from 76.8 kHz (if a 76.8 kHz crystal oscillator is connected), from 160 kHz (if a 160 kHz crystal oscillator is connected), or from the system clock, can be output at the TMOW pin. 1.
Page 193 2. Block diagram Figure 9-1 shows a block diagram of timer A. CWORS ø ø /4 ø ø ø /128 ø ø TMOW ø/32 ø/8192, ø/4096, ø/2048, ø/16 ø/512, ø/256, ø/128, ø/8 ø/32, ø/8 ø/4 ø IRRTA Notation: TMA: Timer mode register A TCA: Timer counter A IRRTA:...
Page 194: Register Descriptions
4. Register configuration Table 9-3 shows the register configuration of timer A. Table 9-3 Timer A Registers Name Abbrev. Initial Value Address Timer mode register A H'10 H'FFB0 Timer counter A H'00 H'FFB1 Clock stop register 1 CKSTPR1 H'FF H'FFFA Subclock output select register CWOSR H'FE...
Page 195 Bits 7 to 5: Clock output select (TMA7 to TMA5) Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A ø signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode.
Page 196 Bits 3 to 0: Internal clock select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 Bit 2 Bit 1 Bit 0 Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0...
Page 197 2. Timer counter A (TCA) TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA).
Page 198: Timer Operation
4. Subclock Output Select Register (CWOSR) Bit: CWOS — — — — — — — Initial value: Read/Write: — — — — — — — CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin. CWOSR is initialized to H'FE by a reset.
Page 199: Timer A Operation States
2. Time base operation When bit TMA3 in TMA is set to 1, timer A functions as a time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available.
Page 200: Timer C
Timer C 9.3.1 Overview Timer C is an 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer C are given below. • Choice of seven internal clock sources (ø/8192, ø/2048, ø/512, ø/64, ø/16, ø/4, ø /4) or an external clock (can be used to count external events).
Page 201 2. Block diagram Figure 9-2 shows a block diagram of timer C. ø TMIC ø IRRTC Notation: : Timer mode register C : Timer counter C : Timer load register C IRRTC : Timer C overflow interrupt request flag : Prescaler S Figure 9-2 Block Diagram of Timer C 3.
Page 202: Register Descriptions
4. Register configuration Table 9-6 shows the register configuration of timer C. Table 9-6 Timer C Registers Name Abbrev. Initial Value Address Timer mode register C H'18 H'FFB4 Timer counter C H'00 H'FFB5 Timer load register C H'00 H'FFB5 Clock stop register 1 CKSTPR1 H'FF H'FFFA...
Page 203 Bits 6 and 5: Counter up/down control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter. Bit 6 Bit 5 TMC6 TMC5 Description TCC is an up-counter (initial value) TCC is a down-counter Hardware control by UD pin input...
Page 204 2. Timer counter C (TCC) TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write TCC is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC).
Page 205: Timer Operation
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer C is described here. For details of the other bits, see the sections on the relevant modules. Bit 1: Timer C module standby mode control (TCCKSTP) Bit 1 controls setting and clearing of module standby mode for timer C.
Page 206 2. Auto-reload timer operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count.
Page 207: Timer C Operation States
9.3.4 Timer C Operation States Table 9-7 summarizes the timer C operation states. Table 9-7 Timer C Operation States Sub- Sub- Module Operation Mode Reset Active Sleep Watch active sleep Standby Standby Interval Reset Functions Functions Halted Functions/ Functions/ Halted Halted Halted* Halted*...
Page 208: Timer F
Timer F 9.4.1 Overview Timer F is a 16-bit timer with a built-in output compare function. As well as counting external events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH and timer FL).
Page 209 2. Block diagram Figure 9-3 shows a block diagram of timer F. ø IRRTFL TCRF øw/4 TCFL TMIF Toggle circuit Comparator TMOFL OCRFL TCFH Toggle circuit Comparator Match TMOFH OCRFH TCSRF Legend TCRF : Timer control register F IRRTFH TCSRF : Timer control status register F TCFH : 8-bit timer counter FH...
Page 210 3. Pin configuration Table 9-8 shows the timer F pin configuration. Table 9-8 Pin Configuration Name Abbrev. Function Timer F event input TMIF Input Event input pin for input to TCFL Timer FH output TMOFH Output Timer FH toggle output pin Timer FL output TMOFL Output...
Page 211: Register Descriptions
9.4.2 Register Descriptions 1. 16-bit timer counter (TCF) 8-bit timer counter (TCFH) 8-bit timer counter (TCFL) Bit: Initial value: Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL.
Page 212 2. 16-bit output compare register (OCRF) 8-bit output compare register (OCRFH) 8-bit output compare register (OCRFL) OCRF Bit: Initial value: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read/Write: OCRFH OCRFL OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
Page 213 3. Timer control register F (TCRF) Bit: TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value: Read/Write: TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the TMOFH and TMOFL pins.
Page 214 Bit 3: Toggle output level L (TOLL) Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is written. Bit 3 TOLL Description Low level (initial value) High level Bits 2 to 0: Clock select L (CKSL2 to CKSL0) Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event input.
Page 215 4. Timer control/status register F (TCSRF) Bit: OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value: Read/Write: R/(W) * R/(W) * R/(W) * R/(W) * Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Page 216 Bit 5: Timer overflow interrupt enable H (OVIEH) Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows. Bit 5 OVIEH Description TCFH overflow interrupt request is disabled (initial value) TCFH overflow interrupt request is enabled Bit 4: Counter clear H (CCLRH) In 8-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
Page 217 Bit 2: Compare match flag L (CMFL) Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2 CMFL Description Clearing conditions: (initial value) After reading CMFL = 1, cleared by writing 0 to CMFL Setting conditions:...
Page 218: Cpu Interface
Bit 2: Timer F module standby mode control (TFCKSTP) Bit 2 controls setting and clearing of module standby mode for timer F. TFCKSTP Description Timer F is set to module standby mode Timer F module standby mode is cleared (initial value) 9.4.3 CPU Interface TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral...
Page 219 1. Write access Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. Figure 9-4 shows an example in which H'AA55 is written to TCF.
Page 220 2. Read access In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the CPU.
Page 221: Operation
9.4.4 Operation Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can also function as two independent 8-bit timers.
Page 222 2. TCF increment timing TCF is incremented by clock input (internal clock or external event input). a. Internal clock operation Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (ø/32, ø/16, ø/4, or øw/4) created by dividing the system clock (ø or øw). b.
Page 223 4. TCF clear timing TCF can be cleared by a compare match with OCRF. 5. Timer overflow flag (OVF) set timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. 6. Compare match flag set timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value).
Page 224: Application Notes
9.4.5 Application Notes The following types of contention and operation can occur when timer F is used. 1. 16-bit timer mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write.
Page 225 If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped.
Page 226 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). 4. Operate interrupt permission (set IENFH, IENFL to 1). Method 2 1. Set interrupt handling routine time to more than time that calculated with (1) formula. 2.
Page 227: Timer G
Timer G 9.5.1 Overview Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). High-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle.
Page 228 2. Block diagram Figure 9-8 shows a block diagram of timer G. ø Level detector øw/4 ICRGF Noise Edge TMIG canceler detector ICRGR IRRTG Notation: : Timer mode register G : Timer counter G ICRGF : Input capture register GF ICRGR : Input capture register GR IRRTG...
Page 229: Register Descriptions
3. Pin configuration Table 9-11 shows the timer G pin configuration. Table 9-11 Pin Configuration Name Abbrev. Function Input capture input TMIG Input Input capture input pin 4. Register configuration Table 9-12 shows the register configuration of timer G. Table 9-12 Timer G Registers Name Abbrev.
Page 230 TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset. Note: * An input capture signal may be generated when TMIG is modified. 2. Input capture register GF (ICRGF) Bit: ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1...
Page 231 4. Timer mode register G (TMG) Bit: OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value: R/(W) * R/(W) * Read/Write: Note: * Bits 7 and 6 can only be written with 0, for flag clearing. TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
Page 232 Bit 5: Timer overflow interrupt enable (OVIE) Bit 5 selects enabling or disabling of interrupt generation when TCG overflows. Bit 5 OVIE Description TCG overflow interrupt request is disabled (initial value) TCG overflow interrupt request is enabled Bit 4: Input capture interrupt edge select (IIEGS) Bit 4 selects the input capture input signal edge that generates an interrupt request.
Page 233: Noise Canceler
5. Clock stop register 1 (CKSTPR1) S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer G is described here. For details of the other bits, see the sections on the relevant modules.
Page 234 The noise canceler consists of five latch circuits connected in series and a match detector circuit. When the noise cancellation function is not used (NCS = 0), the system clock is selected as the sampling clock When the noise cancellation function is used (NCS = 1), the sampling clock is the internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the rising edge of this clock, and the data is judged to be correct when all the latch outputs match.
Page 235: Operation
9.5.4 Operation Timer G is an 8-bit timer with built-in input capture and interval functions. 1. Timer G functions Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. The operation of these two functions is described below. a.
Page 236 2. Increment timing TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four internal clock sources (ø/64, ø/32, ø/2, or øw/4) created by dividing the system clock (ø) or watch clock (øw). 3. Input capture input timing a.
Page 237 Figure 9-12 shows the timing in this case. Input capture input signal Sampling clock Noise canceler output Input capture signal R Figure 9-12 Input Capture Input Timing (with Noise Cancellation Function) 4. Timing of input capture by input capture input Figure 9-13 shows the timing of input capture by input capture input Input capture signal...
Page 238 5. TGC clear timing TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. Figure 9-14 shows the timing for clearing by both edges. Input capture input signal Input capture signal F Input capture signal R H'00...
Page 239: Application Notes
6. Timer G operation modes Timer G operation modes are shown in table 9-13. Table 9-13 Timer G Operation Modes Module Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby Input capture Reset Functions* Functions* Functions/ Functions/ Functions/ Halted Halted halted* halted*...
Page 240 Table 9-14 Internal Clock Switching and TCG Operation Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from low level to low level Clock before switching Clock after switching Count clock Write to CKS1 and CKS0 Goes from low level to high level Clock before switching...
Page 241 Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from high level to high level Clock before switching Clock before switching Count clock Write to CKS1 and CKS0 Note: The switchover is seen as a falling edge, and TCG is incremented. 2.
Page 242 Table 9-15 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching, and Conditions for Their Occurrence Input Capture Input Signal Input Edge Conditions Generation of rising edge When TMIG is modified from 0 to 1 while the TMIG pin is high When NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceler...
Page 243 When the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use. Figure 9-15 shows the procedure for port mode register manipulation and interrupt request flag clearing.
Page 244: Timer G Application Example
9.5.6 Timer G Application Example Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 should both be set to 1 in TMG. Figure 9-16 shows an example of the operation in this case.
Page 245: Watchdog Timer
Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1. Features Features of the watchdog timer are given below.
Page 246: Register Descriptions
3. Register configuration Table 9-17 shows the register configuration of the watchdog timer. Table 9-17 Watchdog Timer Registers Name Abbrev. Initial Value Address Timer control/status register W TCSRW H'AA H'FFB2 Timer counter W H'00 H'FFB3 Clock stop register 2 CKSTP2 H'FF H'FFFB Port mode register 3...
Page 247 Bit 6: Timer counter W write enable (TCWE) Bit 6 controls the writing of data to TCW. Bit 6 TCWE Description Data cannot be written to TCW (initial value) Data can be written to TCW Bit 5: Bit 4 write inhibit (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW.
Page 248 Bit 2: Watchdog timer on (WDON) Bit 2 enables watchdog timer operation. Bit 2 WDON Description Watchdog timer operation is disabled (initial value) Clearing conditions: Reset, or when TCSRWE = 1 and 0 is written in both B2WI and WDON Watchdog timer operation is enabled Setting conditions: When TCSRWE = 1 and 0 is written in B2WI and 1 is written in...
Page 249 2. Timer counter W (TCW) TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input clock is ø/8192 or øw/32. The TCW value can always be written or read by the CPU. When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to 1 in TCSRW.
Page 250: Timer Operation
4. Port mode register 3 (PMR3) PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3 pins. Only the bit relating to the watchdog timer is described here. For details of the other bits, see section 8, I/O Ports.
Page 251: Watchdog Timer Operation States
Figure 9-18 shows an example of watchdog timer operations. Example: ø = 2 MHz and the desired overflow period is 30 ms. 2 × 10 × 30 × 10 –3 = 7.3 8192 The value set in TCW should therefore be 256 – 8 = 248 (H'F8). TCW overflow H'FF H'F8...
Page 253: Section 10 Serial Communication Interface
Section 10 Serial Communication Interface 10.1 Overview The H8/3937 Series and H8/3937R Series are provided with two serial communication interface (SCI) channels plus one SCI channel for on-chip FLEX™ decoder interfacing. The functions of the three SCI channels are summarized in table 10-1.
Page 254: Sci1 [Chip Internal Function]
10.2 SCI1 [Chip Internal Function] 10.2.1 Overview Serial communication interface 1 (SCI1) can carry out 8-bit or 16-bit serial data transfer in synchronous mode. SCI1 is an internal function that performs interfacing to the FLEX™ decoder incorporated in the chip. It cannot be connected to an IC outside the chip for data communication use.
Page 255 2. Block Diagram Figure 10-1 shows a block diagram of SCI1. ø ø SCK1 SCR1 SCSR1 Transmit/receive control circuit Transfer bit counter SDRU SDRL IRRS1 Notation: SCR1: Serial control register 1 SCSR1: Serial control status register 1 SDRU: Serial data register U SDRL: Serial data register L IRRS1:...
Page 256: Register Descriptions
3. I/O configuration Table 10-2 shows the SCI1 I/O configuration. Table 10-2 SCI1 I/O Configuration Name Abbrev. Function SCI1 clock SCI1 clock input/output SCI1 data input Input SCI1 receive data input SCI1 data output Output SCI1 transmit data output 4. Register configuration Table 10-3 shows the SCI1 register configuration.
Page 257 Bits 7 and 6: Operating mode select 1 and 0 (SNC1, SNC0) Bits 7 and 6 select the operating mode. Bit 7 Bit 6 SNC1 SNC0 Description 8-bit synchronous mode (initial value) 16-bit synchronous mode Continuous clock output mode* Reserved* Notes: 1.
Page 258 Bit 3: Clock source select 3 (CKS3) Bit 3 selects the clock source to be supplied and sets the SCK to input or output mode. Bit 3 CKS3 Description Clock source is prescaler S, SCK is output (initial value) Clock source is external clock, SCK is input* Note: SCI1 is an internal function that performs interfacing to the on-chip FLEX™...
Page 259 Bit 7: Reserved bit Bits 7 is reserved; it is always read as 1 and cannot be modified. Bit 6: Extension data bit (SOL) The SOL bit changes the output level of the SO . When read, SOL returns the output level of the .
Page 260 Bit 1: Tail mark transmission flag (MTRF) When MRKON = 1, bit 1 indicates that a tail mark is being transmitted. MTRF is a read-only bit, and cannot be modified. Bit 1 MTRF Description Idle state, or 8-bit/16-bit data transfer in progress (initial value) Tail mark transmission in progress Bit 0: Start flag (STF)
Page 261 4. Serial data register L (SDRL) SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write SDRL is an 8-bit read/write register used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (while SDRU is used for the upper 8 bits).
Page 262: Operation
Bit 7: SCI1 module standby mode control (S1CKSTP) Bit 7 controls setting and clearing of module standby mode for SCI1. Bit 7 S1CKSTP Description SCI1 is set to module standby mode* SCI1 module standby mode is cleared (initial value) Note: Setting to module standby mode resets SCR1, SCSR1, SDRU and SDRL.
Page 263 3. Data transfer operations Transmitting: The procedure for transmitting data is as follows. (1) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO1 and SCK1 functions. (2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to CKS0.
Page 264: Interrupt Source
Simultaneous transmitting and receiving: The procedure for simultaneously transmitting and receiving data is as follows. (1) Set SO1, SI1, and SCK1 all to 1 in PMR2 to designate the SO1, SI1, and SCK1 functions. (2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to CKS0.
Page 265: Application Note
10.2.5 Application Note (1) Conditions for use of SCI1 in subactive mode and subsleep mode In subactive or subsleep mode, SCI1 can be used only when the CPU operation clock is ø (2) Confirming the end of serial transfer Do not read or write to SCSR1 during serial transfer. The following two methods can be used to confirm the end of serial transfer: (a) Using SCI1 interrupt exception handling Set the IENS1 bit to 1 in IENR1 and execute interrupt exception handling.
Page 266: Sci3
SCI3 10.3.1 Overview In addition to SCI1, the H8/3937 Series and H8/3937R Series have two serial communication interfaces, SCI31 and SCI32, with identical functions. In this manual, the generic term SCI3 is used to refer to both of these SCIs.
Page 267  Synchronous mode Serial data communication is synchronized with a clock. In his mode, serial data can be exchanged with another LSI that has a synchronous communication function. Data length 8 bits Receive error detection Overrun errors • Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously.
Page 268 2. Block diagram Figure 10-3 shows a block diagram of SCI3. Internal clock (ø/64, ø/16, øw/2, ø) External Baud rate generator clock Clock Transmit/receive SCR3 control circuit SPCR Interrupt request (TEI, TXI, RXI, ERI) Notation: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register...
Page 269 3. Pin configuration Table 10-4 shows the SCI3 pin configuration. Table 10-4 Pin Configuration Name Abbrev. Function SCI3 clock SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output 4.
Page 270: Register Descriptions
10.3.2 Register Descriptions 1. Receive shift register (RSR) Read/Write — — — — — — — — RSR is a register used to receive serial data. Serial data input to RSR from the RXD pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically.
Page 271 3. Transmit shift register (TSR) Read/Write — — — — — — — — TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD pin in order, starting from the LSB (bit 0).
Page 272 5. Serial mode register (SMR) STOP CKS1 CKS0 Initial value Read/Write SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, watch or module standby mode.
Page 273 Bit 5: Parity enable (PE) Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. Bit 5 Description Parity bit addition and checking disabled*...
Page 274 Bit 3: Stop bit length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added.
Page 275 Bits 1 and 0: Clock select 1 and 0 (CKS1, CKS0) Bits 1 and 0 choose ø/64, ø/16, ø/2, or ø as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate register (BRR).
Page 276 Bit 7: Transmit interrupt enable (TIE) Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when transmit data is transferred from the transmit data register (TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to 1. TXI can be released by clearing bit TDRE or bit TIE to 0.
Page 277 Bit 4: Receive enable (RE) Bit 4 selects enabling or disabling of the start of receive operation. Bit 4 Description Receive operation disabled* (RXD pin is I/O port) (initial value) Receive operation enabled* (RXD pin is receive data pin) Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state.
Page 278 Bit 2: Transmit end interrupt enable (TEIE) Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to be sent. Bit 2 TEIE Description Transmit end interrupt request (TEI) disabled (initial value) Transmit end interrupt request (TEI) enabled*...
Page 279 7. Serial status register (SSR) TDRE RDRF TEND MPBR MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Note: * Only a write of 0 for flag clearing is possible. SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and multiprocessor bits.
Page 280 Bit 6: Receive data register full (RDRF) Bit 6 indicates that received data is stored in RDR. Bit 6 RDRF Description There is no receive data in RDR (initial value) Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF When RDR data is read by an instruction There is receive data in RDR Setting conditions:...
Page 281 Bit 4: Framing error (FER) Bit 4 indicates that a framing error has occurred during reception in asynchronous mode. Bit 4 Description Reception in progress or completed* (initial value) Clearing conditions: After reading FER = 1, cleared by writing 0 to FER A framing error has occurred during reception Setting conditions: When the stop bit at the end of the receive data is checked for a value...
Page 282 Bit 2: Transmit end (TEND) Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified. Bit 2 TEND Description Transmission in progress Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE When data is written to TDR by an instruction...
Page 283 8. Bit rate register (BRR) BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time.
Page 284 Table 10-6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) 10 MHz 16 MHz Bit Rate Error Error (bit/s) –0.25 2 –0.02 0.16 0.16 –0.35 2 0.16 0.16 –0.79 — — — 0.16 — — — 0.16 1200 0.16 0.16...
Page 285 Table 10-7 Relation between n and Clock SMR Setting Clock CKS1 CKS0 ø ø /ø ø/16 ø/64 Notes: 1. ø /2 clock is selected in active (medium- and high-speed) or sleep (medium- and high- speed) mode. 2. ø clock is selected in subactive or subsleep mode. SCI3 can be used only when the ø...
Page 286 Table 10-9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1) 38.4 kHz 2 MHz 4 MHz Bit Rate (bit/s) n Error Error Error — — — — — — — — — — — — — — —...
Page 287 Table 10-9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2) 10 MHz 16 MHz Bit Rate (bit/s) n Error Error — — — — — — — — — — — — — — — — — —...
Page 288 Table 10-10 Relation between n and Clock SMR Setting Clock CKS1 CKS0 ø ø /ø ø/16 ø/64 Notes: 1. ø /2 clock is selected in active (medium- and high-speed) or sleep (medium- and high- speed) mode. 2. ø clock is selected in subactive or subsleep mode. SCI3 can be used only when the ø...
Page 289 9. Clock stop register 1 (CKSTPR1) S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the sections on the relevant modules.
Page 290 10. Serial Port Control Register (SPCR) — — SPC32 SPC31 SCINV3 SCINV2 SCINV1 SCINV0 Initial value Read/Write — — SPCR is an 8-bit readable/writable register that performs RXD , RXD , TXD , and TXD input/output data inversion switching. SPCR is initialized to H'C0 by a reset. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved;...
Page 291 Bit 2: RXD pin input data inversion switch Bit 2 specifies whether or not RXD pin input data is to be inverted. Bit 2 SCINV2 Description input data is not inverted (initial value) input data is inverted Bit 1: TXD pin output data inversion switch Bit 1 specifies whether or not TXD pin output data is to be inverted.
Page 292: Operation
10.3.3 Operation 1. Overview SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10-11.
Page 293 Table 10-11 SMR Settings and Corresponding Data Transfer Formats Data Transfer Format bit 7 bit 6 bit 2 bit 5 bit 3 Data Multiprocessor Parity Stop Bit STOP Mode Length Length Asynchronous 8-bit data No 1 bit mode 2 bits 1 bit 2 bits 7-bit data...
Page 294 Table 10-12 SMR and SCR3 Settings and Clock Source Selection SCR3 bit 7 bit 1 bit 0 Transmit/Receive Clock COM CKE1 CKE0 Mode Clock Source SCK Pin Function Asynchronous Internal I/O port (SCK pin not used) mode Outputs clock with same frequency as bit rate External Outputs clock with frequency 16 times bit rate Synchronous...
Page 295 c. Interrupts and continuous transmission/reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10-13. Table 10-13 Transmit/Receive Interrupts Interrupt Flags Interrupt Request Conditions Notes RDRF When serial reception is performed The RXI interrupt routine reads the normally and receive data is transferred receive data transferred to RDR...
Page 296 RSR (reception in progress) RSR↑ (reception completed, transfer) RDRF ← 1 RDRF = 0 (RXI request when RIE = 1) Figure 10-4 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) TSR (transmission in progress) TSR↓ (transmission completed, transfer) TDRE ←...
Page 297 2. Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication.
Page 298 Table 10-14 Data Transfer Formats (Asynchronous Mode) Serial Data Transfer Format and Frame Length STOP 10 11 12 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 5-bit data STOP 5-bit data STOP STOP...
Page 299 b. Clock Either an internal clock generated by the baud rate generator or an external clock input at the pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10-12 for details on clock source selection.
Page 300 Figure 10-7 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 Set clock selection in SCR3. Be sure to Set bits CKE1 clear the other bits to 0. If clock output and CKE0 is selected in asynchronous mode, the clock is output immediately after setting...
Page 301 • Transmitting Figure 10-8 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then write transmit data to the transmit...
Page 302 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 303 • Receiving Figure 10-10 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bits OER, Read bits OER, PER, and FER in the PER, FER in SSR serial status register (SSR) to determine if there is an error.
Page 304 If a receive error has Start receive occurred, read bits OER, error processing Overrun error PER, and FER in SSR to processing identify the error, and after carrying out the necessary error processing, ensure OER = 1? that bits OER, PER, and FER are all cleared to 0.
Page 305 SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10-14. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received.
Page 306 Figure 10-11 shows an example of the operation when receiving in asynchronous mode. Start Receive Parity Stop Start Receive Parity Stop Mark state data data (idle state) Serial data 1 frame 1 frame RDRF RXI request RDRF 0 start bit ERI request in operation cleared to 0...
Page 307 a. Data transfer format The general data transfer format in synchronous communication is shown in figure 10-12. Serial clock Serial Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 data Don't Don't 8 bits care care One transfer data unit (character or frame)
Page 308 c. Data transfer operations • SCI3 initialization Data transfer on SCI3 first of all requires that SCI3 be initialized as described in “SCI initialization” under 10.3.3, 2. c. Data transfer operations, and shown in figure 10-7. • Transmitting Figure 10-13 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3.
Page 309 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 310 • Receiving Figure 10-15 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bit OER Read bit OER in the serial status register in SSR (SSR) to determine if there is an error. If an overrun error has occurred, execute overrun error processing.
Page 311 SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR.
Page 312 • Simultaneous transmit/receive Figure 10-17 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR Read the serial status register (SSR) and Read bit TDRE check that bit TDRE is set to 1, then write in SSR...
Page 313 4. Multiprocessor Communication Function The multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. Serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data).
Page 314 Sender Communication line Receiver A Receiver B Receiver C Receiver D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle Data transmission cycle (specifying the receiver) (sending data to the receiver specified buy the ID) MPB: Multiprocessor bit...
Page 315 Start Sets bits SPC31 and SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR).
Page 316 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 317 Start Set bit MPIE to 1 in SCR3. Set bit MPIE to 1 in SCR3 Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has Read bits OER occurred, execute receive error processing.
Page 318 Start receive error processing Overrun error processing OER = 1? Break? FER = 1? Framing error processing Clear bits OER and FER to 0 in SSR End of receive error processing Figure 10-21 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10-22 shows an example of the operation when receiving using the multiprocessor format.
Page 319 Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI request RDRF cleared No RXI request operation MPIE cleared to 0 RDR retains to 0 previous state User RDR data read When data is not...
Page 320: Interrupts
10.3.4 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10-16. Table 10-16 SCI3 Interrupt Requests Interrupt Abbreviation...
Page 321: Application Notes
10.3.5 Application Notes The following points should be noted when using SCI3. 1. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically.
Page 322 3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is set and bit PER may also be set.
Page 323 16 clock pulses 8 clock pulses 15 0 15 0 Internal basic clock Receive data Start bit (RXD3x) Synchronization sampling timing Data sampling timing Figure 10-23 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1).
Page 324 7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred.
Page 325 9. Cautions on Switching of SCK Pin Function If the function of the SCK pin is switched from clock output to I/O port after using the SCI3 in clock synchronization mode, the low level is output in a moment (1/2 of the system clock ø) at the pin function switching.
Page 327: Section 11 A/D Converter
Section 11 A/D Converter 11.1 Overview The H8/3937 Series and H8/3937R Series include on-chip a resistance-ladder-based successive- approximation analog-to-digital converter, and can convert up to 8 channels of analog input. 11.1.1 Features The A/D converter has the following features. • 10-bit resolution •...
Page 328: Block Diagram
11.1.2 Block Diagram Figure 11-1 shows a block diagram of the A/D converter. ADTRG Multiplexer ADSR Com- Control logic parator – Reference voltage ADRRH ADRRL IRRAD Notation: AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D conversion end interrupt request flag Figure 11-1 Block Diagram of the A/D Converter...
Page 329: Pin Configuration
11.1.3 Pin Configuration Table 11-1 shows the A/D converter pin configuration. Table 11-1 Pin Configuration Name Abbrev. Function Analog power supply Input Power supply and reference voltage of analog part Analog ground Input Ground and reference voltage of analog part Analog input 0 Input Analog input channel 0...
Page 330: Register Descriptions
11.2 Register Descriptions 11.2.1 A/D Result Registers (ADRRH, ADRRL) ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 — — — — — — Initial value — — — — — — fixed fixed fixed fixed fixed fixed fixed fixed fixed fixed...
Page 331 Bit 7: Clock select (CKS) Bit 7 sets the A/D conversion speed. Bit 7 Conversion Time Conversion Period ø = 1 MHz ø = 5 MHz 62/ø (initial value) 62 µs 12.4 µs 31/ø 31 µs — Note: Operation is not guaranteed if the conversion time is less than 12.4 µs. Set bit 7 for a value of at least 12.4 µs.
Page 332: A/D Start Register (Adsr)
Bits 3 to 0: Channel select (CH3 to CH0) Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected (initial value) Reserved...
Page 333: Clock Stop Register 1 (Ckstpr1)
Bit 7: A/D start flag (ADSF) Bit 7 controls and indicates the start and end of A/D conversion. Bit 7 ADSF Description Read: Indicates the completion of A/D conversion (initial value) Write: Stops A/D conversion Read: Indicates A/D conversion in progress Write: Starts A/D conversion Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved;...
Page 334: Operation
11.3 Operation 11.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 10- bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
Page 335: A/D Converter Operation Modes
11.3.3 A/D Converter Operation Modes A/D converter operation modes are shown in table 11-3. Table 11-3 A/D Converter Operation Modes Operation Module Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby Reset Functions Functions Held Held Held Held Held ADSR Reset Functions Functions Held Held...
Page 336 6. The A/D interrupt handling routine ends. If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 11-4 and 11-5 show flow charts of procedures for using the A/D converter. Interrupt (IRRAD) Set * IENAD...
Page 337 Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR ADSF = 0? Read ADRRH/ADRRL data Perform A/D conversion? Figure 11-4 Flow Chart of Procedure for Using A/D Converter (Polling by Software)
Page 338 Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Clear bit IRRAD to 0 in IRR2 Read ADRRH/ADRRL data Perform A/D conversion? Figure 11-5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used)
Page 339: Application Notes
11.6 Application Notes • Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. • Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy.
Page 341: Section 12 Flex Roaming Decoder
Section 12 FLEX Roaming Decoder II The contents of this section apply to the FLEX™ Roaming Decoder. Note that underlining in the text indicates differences in specification from the FLEX™ Non-Roaming Decoder. 12.1 Overview Its primary function is to process information received and demodulated from a FLEX radio paging channel, select messages addressed to the paging device and communicate the message information to the host.
Page 342: System Block Diagram
FLEX channel, and fully interpreting the code words that are passed to the host from the FLEX decoder. Additional Information: Additional Information on the FLEX protocol decoder chip set and FLEXstack™ software can be found at the following website: http://www.hitachi.co.jp/Sicd/English/Products/micom/stack/stack.html. 12.1.2 System Block Diagram Synthesizer Programming Control User...
Page 343 Synthesizer Programming Control User Interface Receiver Control Receiver Audio This LSI 38.4 clock EXTS1 Audio to Digital EXTS0 Convertor 76.8 kHz Oscillator Low Battery LOBAT Detector Figure 12-2 Example Block Diagram Using External Demodulator The FLEX decoder can also be configured to connect to a receiver capable of converting a 4 level audio signal into a 2 bit digital signal.
Page 344: 12.1.3 Functional Block Diagram
12.1.3 Functional Block Diagram S1-S7 S1-S7 Receiver Control S0/IFIN Internal Control Demodulator & IFIN Unit Data Slicer EXTS0 EXTS1 Symbol Sync Noise Detector SYMCLK 76.8 kHz ø TESTD Sync or 160 kHz Correlator Oscillator External RESET Control Unit LOBAT CLKOUT Clock Generator De-interleaver...
Page 345: Spi Packets
12.2 SPI Packets All data communicated between the FLEX decoder and the host MCU is transmitted on the SPI in 32-bit packets. Each packet consists of an 8-bit ID followed by 24 bits of information. The FLEX decoder uses the SPI bus in full duplex mode. In other words, whenever a packet communication occurs, the data in both directions is valid packet data.
Page 346: Packet Communication Initiated By The Flex Decoder
The host must transition the SS pin from high to low to begin each 32-bit packet. The FLEX decoder must see a negative transition on the SS pin in order for the host to initiate each packet communication. 12.2.2 Packet Communication Initiated by the FLEX decoder Refer to figure 12-5.When the FLEX decoder has a packet for the host to read, the following occurs: 1.
Page 347 READY MOSI D1 D0 D1 D0 D1 D0 MISO D1 D0 D1 D0 D1 D0 High impedance state Figure 12-6 Multiple Packet Communications Initiated by the FLEX decoder with No De-select...
Page 348: Host-To-Decoder Packet Map
12.2.3 Host-to-Decoder Packet Map The upper 8 bits of a packet comprise the packet ID. The following table describes the packet ID’s for all of the packets that can be sent to the FLEX decoder from the host. Table 12-1 Host-to-Decoder Packet ID Map Packet ID (Hexadecimal) Packet Type...
Page 349 Packet ID (Hexadecimal) Packet Type Frame Assignment (Frames 32 through 47) Frame Assignment (Frames 16 through 31) Frame Assignment (Frames 0 through 15) 28 - 77 Reserved (Host should never send) User Address Enable 79 - 7F Reserved (Host should never send) User Address Assignment (User address 0) User Address Assignment (User address 1) User Address Assignment (User address 2)
Page 350: Decoder-To-Host Packet Map
12.2.4 Decoder-to-Host Packet Map The following table describes the packet ID’s for all of the packets that can be sent to the host from the FLEX decoder. Table 12-2 Decoder-to-Host Packet ID Map Packet ID (Hexadecimal) Packet Type Block Information Word Address 02- 57 Vector or Message (ID is word number in frame)
Page 351 1F is sent to the decoder IC, the value sent in the 24 information bits is exclusive-or’ed with the internal checksum register, the result is stored back to the checksum register, and the FLEX decoder is disabled. If a Checksum Packet is sent and the CV bits match the bits in the checksum register, the FLEX decoder is enabled.
Page 352 RESET Decoder disables itself Decoder initializes checksum register to Part ID value Decoder initiates Part ID Packet Decoder waits for SPI packet from host Checksum Packet? Decoder disables itself Decoder enabled? Decoder sets checksum register to the XOR of the packet data bits with the checksum register bits Packet data...
Page 353: Configuration Packet
12.3.2 Configuration Packet The Configuration Packet defines a number of different configuration options for the FLEX decoder. Proper operation is not guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control Packet is set). The ID of the Configuration Packet is 1. Table 12-4 Configuration Packet Bit Assignments Bit 7 Bit 6...
Page 354 Frequency Difference +/- 300 ppm +/- 150 ppm +/- 75 ppm +/- 0 ppm PCE: Partial Correlation Enable. When this bit is set, partial correlation of addresses is enabled. When partial correlation is enabled, the FLEX decoder will shutdown the receiver before the end of the last FLEX block which contains addresses if it can determine that none of the addresses in that FLEX block will match any enabled address in the FLEX decoder.
Page 355 COD: Clock Output Disable. When this bit is clear, a 38.4 kHz or 40 kHz (depending on the values of IDE and DFC) signal will be output on the CLKOUT pin. When this bit is set, the CLKOUT pin will be driven low. Note that setting and clearing this bit can cause pulses on the CLKOUT pin that are less than one half the clock period.
Page 356: Control Packet
12.3.3 Control Packet The Control Packet defines a number of different control bits for the FLEX decoder. The ID of the Control Packet is 2. Table 12-5 Control Packet Bit Assignments Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 357: All Frame Mode Packet
MTC: Minute Timer Clear. Setting this bit will cause the one minute timer to restart from 0. EAE: End of Addresses Enable. When this bit is set, the EA bit in the Status Packet will be set immediately after the FLEX decoder decodes the last address word in the frame if any of the enabled FLEX decoder addresses was detected in the frame.
Page 358 See 12.5.4, Operation of a Temporary Address for details. The FLEX decoder will increment the all frame mode counter whenever an alphanumeric, HEX / binary, or secure vector is received. When the host determines that a message associated with a temporary address, or a fragmented message has ended, then the appropriate temporary address counter or all frame mode counter should be decremented by writing an All Frame Mode Packet to the FLEX decoder in order to exit the all frame mode, thereby improving battery life.
Page 359: Operator Messaging Address Enable Packet
12.3.5 Operator Messaging Address Enable Packet The contents of this section apply to the FLEX™ Roaming Decoder. They are not applicable to the FLEX™ Non-Roaming Decoder. The operator messaging address enable packet is used to enable and disable the built-in FLEX operator messaging addresses.
Page 360 IRS: Ignore Re-synchronization Signal. When this bit is set, the FLEX decoder will not go asynchronous when detecting an Ar or Ar signal during searches for A-words. It will merely report that the re-synchronization signal was received by setting RSR to 1 in the Roaming Status packet. This allows the host to decide what to do when the paging device is synchronous to more than one channel and only one channel is sending the re-synchronization signal.
Page 361 Roaming Status Packet. This bit is set by the host, and cleared by the FLEX decoder once it has been processed. If the time comes for the FLEX decoder to warm up automatically or the SAS bit is set while an SND is being processed, the noise detect will be abandoned and the abandoned noise detect result (NDR = 01) will be sent in the Roaming Status Packet.
Page 362: Timing Control Packet
Missing Frame Data Reported Never Only during frames 0 through 3 Only during frames 0 through 7 Always MCO: Maximum Carry On. The value of these bits sets the maximum carry on that the FLEX decoder will follow. For example, if the FLEX decoder receives a carry on of 3 over the air and MCO is set to 1, the FLEX decoder will only carry on for one frame.
Page 363: Receiver Line Control Packet
12.3.8 Receiver Line Control Packet This packet gives the host control over the settings on the receiver control lines (S0-S7) in all modes except reset. In reset, the receiver control lines are in high impedance settings. The ID for the Receiver Line Control Packet is 15 (decimal). Table 12-10 Receiver Line Control Packet Bit Assignments Bit 7 Bit 6...
Page 364 LBC: Low Battery Check. If this bit is set, the FLEX decoder will check the status of the LOBAT port just before leaving this receiver state. (value after reset=0) CLS: Control Line Setting. This is the value to be output on the receiver control lines (S0-S7) for this receiver state.
Page 365 ST: Step Time. This is the time the FLEX decoder is to wait before applying the next state’s receiver control value to the receiver control lines. The setting is in steps of 625µs. Valid values are 625µs (ST=01) to 79.375ms (ST=7F in hexadecimal). (value after reset=625µs) 3.
Page 366 s: Setting Number. Receiver control setting for which this packet’s values are to be applied. The following truth table shows the names of each of the values for s that apply to this packet. Setting Name 0 1 1 1 1600sps Sync 1 0 0 0 3200sps Data...
Page 367: 12.3.10 Frame Assignment Packets
ST: Step Time. This is the time the FLEX decoder is to wait before applying the next state’s receiver control value to the receiver control lines. The setting is in steps of 625µs. Valid values are 625µs (ST=01) to 39.375ms (ST=3F in hexadecimal). (value after reset=625µs) 12.3.10 Frame Assignment Packets The FLEX protocol defines that each address of a FLEX pager is assigned a home frame and a battery cycle.
Page 368: 12.3.11 User Address Enable Packet
0 0 0 Frame 127 Frame 112 0 0 1 Frame 111 Frame 96 0 1 0 Frame 95 Frame 80 0 1 1 Frame 79 Frame 64 1 0 0 Frame 63 Frame 48 1 0 1 Frame 47 Frame 32 1 1 0 Frame 31...
Page 369: User Address Assignment Packets
12.3.12 User Address Assignment Packets The FLEX decoder has 16 user address words. Each word can be programmed to be a short address, part of a long address, or the first part of a network ID . The addresses are configured using the Address Assignment Packets.
Page 370: Decoder-To-Host Packet Descriptions
12.4 Decoder-to-Host Packet Descriptions The following sections describe the packets of information that will be sent from the FLEX decoder to the host. In all cases the packets are sent MSB first (bit 7 of byte 3 = bit 31 of the packet = MSB).
Page 371: Block Information Word Packet
12.4.1 Block Information Word Packet The Block Information Field is the first field following the synchronization codes of the FLEX protocol. This field contains information about the frame such as number of addresses and messages, information about current time, the channel ID, channel attributes, etc. The first block information word of each phase is used internally to the FLEX decoder and is never transmitted to the host with the exception of the system collapse which is sent to the host when the FLEX decoder is in manual collapse mode.
Page 372: Address Packet
Description Local ID, Coverage Zone Month, Day, Year Second, Minute, Hour Reserved by FLEX protocol for future use Reserved by FLEX protocol for future use System Message Reserved by FLEX protocol for future use Country Code, Traffic Management Flags Notes: 1. Will be decoded only if the ABI bit is set. 2.
Page 373: Vector Packet
address words. Values 128 through 143 correspond to the 16 temporary addresses . Values 144 through 159 correspond to the 16 operator messaging addresses. For long addresses, the address detect packet will only be sent once and the index will refer to the second word of the address. TOA: Tone Only Address.
Page 374 bit errors are detected (via BCH calculations, parity calculations, check character calculations, or value validation) in the vector word the e bit will be set and the message words will not be sent. 1. Numeric Vector Packet Table 12-21 Numeric Vector Packet Bit Assignments Bit 7 Bit 6 Bit 5...
Page 375 2. Short Message / Tone Only Vector Table 12-22 Short Message / Tone Only Vector Packet Bit Assignments Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 Byte 2 Byte 1 Byte 0 V: 010 for a Short Message / Tone Only Vector WN: Word number of vector (2 - 87 decimal).
Page 376 3. HEX / Binary, Alphanumeric, and Secure Message Vector Table 12-23 HEX / Binary, Alphanumeric, and Secure Message Vector Packet Bit Assignments Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 Byte 2 Byte 1 Byte 0...
Page 377 4. Short Instruction Vector Table 12-24 Short Instruction Vector Packet Bit Assignments Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 Byte 2 Byte 1 Byte 0 V: 001 for a Short Instruction Vector WN: Word number of vector (2 - 87 decimal).
Page 378: Message Packet
i: Instruction type. These bits define the meaning of the d bits in this packet. x: Unused bits. The value of these bits is not guaranteed. 12.4.4 Message Packet The Message Field follows the Vector Field in the FLEX protocol. It contains the message data, checksum information, and may contain fragment numbers and message numbers.
Page 379 Table 12-26 Roaming Status Packet Bit Assignments Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 Byte 2 Byte 1 Byte 0 RSR: Re-synchronization Signal Received. Set when the FLEX decoder detected a re- synchronization signal and the host configured the FLEX decoder to ignore it via the IRS bit in the roaming control packet.
Page 380 n: Network bit value. When NBU is set, this is the value of the n bit in the last received frame information word. NDR: Noise Detect Result. These bits indicate the result of a noise detect. The results of noise detects initiated by setting the SND bit in the roaming control packet will always be reported.
Page 381: Receiver Shutdown Packet
12.4.6 Receiver Shutdown Packet The contents of this section apply to the FLEX™ Roaming Decoder. They are not applicable to the FLEX™ Non-Roaming Decoder. The Shutdown Packet is sent in both synchronous and asynchronous mode. It is designed to indicate to the host that the receiver is turned off and how much time there is until the FLEX decoder will automatically turn it back on.
Page 382: Status Packet
12.4.7 Status Packet The Status Packet contains various types of information that the host may require. The Status Packet will be sent to the host whenever the FLEX decoder is polled and has no other data to send. The FLEX decoder can also prompt the host to read the Status Packet due to events for which the FLEX decoder was configured to send it (see 12.3.2, Configuration Packet and 12.3.3, Control Packet for a detailed description of the bits).
Page 383 collapse). This bit is initialized to 0 when the FLEX decoder is reset and when it is turned off by clearing the ON bit in the Control Packet. LB: Low Battery. Set to the value last read from the LOBAT pin. The host controls when the LOBAT pin is read via the Receiver Control Packets.
Page 384: Part Id Packet
x: Unused bits. The value of these bits is not guaranteed. 12.4.8 Part ID Packet The Part ID Packet is sent by the FLEX decoder whenever the FLEX decoder is disabled due to the checksum feature. See 12.3.1, Checksum Packet for a description of the checksum feature. Since the FLEX decoder is disabled after reset, this is the first packet that will be received by the host after reset.
Page 385 FLEX Roaming Decoder II Motorola Semiconductor Products Sector 00 03 0A FLEX Roaming Decoder II Texas Instruments 00 04 01 FLEX Numeric Decoder Texas Instruments 00 01 15 FLEX Alphanumeric Decoder II Hitachi 00 03 15 FLEX Roaming Decoder II Hitachi...
Page 386: Application Notes
12.5 Application Notes 12.5.1 Receiver Control Introduction: The FLEX decoder has 8 programmable receiver control lines (S0-S7). The host has control of the receiver warm up and shut down timing as well as all of the various settings on the control lines through configuration registers on the FLEX decoder. The configuration registers for most settings allow the host to configure what setting is applied to the control lines, how long to apply the setting, and if the LOBAT input pin is polled before changing from the setting.
Page 387 The receiver warm up sequence while decoding when all warm up settings are enabled is shown in figure 12-9. 160 ms Warm Up Warm Up Warm Up Warm Up Warm Up Warm Up Off Time Time 1 Time 2 Time 3 Time 4 Time5 RECEIVER...
Page 388 4. Receiver Shut Down Sequence The FLEX decoder allows for up to 3 steps associated with shutting down the receiver. When the FLEX decoder decides to turn off the receiver, the first shut down setting, if enabled, is applied to the receiver control lines for the corresponding shut down time.
Page 389: Message Building
• 3200sps Data Setting:This setting is applied after the FLEX decoder has found the C or C sync word in a 3200 symbols per second frame. Some examples of how these settings will be used in the FLEX decoder are shown in figure 12-12. Frame FLEX SIGNAL Block 10...
Page 390 (WN 12 - 15). The third message is in phase C and has a 2 word long address (WN 5 - 6) followed by a vector (WN 10) and three message words. Since the third message is sent on a long address, the first message word (WN 11) begins immediately after the vector.
Page 391: Building A Fragmented Message
Table 12-31 FLEX DECODER PACKET SEQUENCE PACKET WORD PACKET TYPE PHASE NUMBER COMMENT ADDRESS N.A. (7) Address 1 has a vector located at WN 7 ADDRESS N.A. (8) Address 2 has a vector located at WN 8 VECTOR Vector for Address 1: Message Words located at WN = 9 to 11, phase A N.A.
Page 392 Additional fragments can be expected when the “continue bit” in the 1st Message Word is set. This causes the pager to examine every following frame for an additional fragment until the last fragment with the continue bit reset is found. The only requirement relating to the placement in time of the remaining fragments is that no more than 32 frames (1 minute) or 128 frames (4 minutes) as indicated by the service provider may pass between fragment receptions.
Page 393 packets decrement the count for the first fragment and the last fragment. This dec-rements the all frame counter to zero, if no other fragmented messages, temporary addresses are pending and the FAF bit is clear in the All Frame Mode Register, the FLEX decoder returns to normal operation.
Page 394: Operation Of A Temporary Address
Table 12-33 Alphanumeric Message with fragmentation All Frame PACKET PACKET TYPE PHASE Counter COMMENT ADDRESS 1 Address 1 is received VECTOR 1 Vector = Alphanumeric Type MESSAGE Message Word received “C” bit = 1, Message is fragmented, more expected STATUS End of Frame Indication (EOF = 1) ADDRESS 1 Address 1 is received...
Page 395 The following describes the sequence of events between the Host and the FLEX decoder required to handle a temporary address: • Following an Address Packet, the host will receive a Vector Packet with V = 001 and i = 000 or 010 (a Short Instruction Vector indicating a temporary address has been assigned to this pager).
Page 396: Using The Receiver Shutdown Packet
• The above operation is repeated for every temporary address. 12.5.5 Using the Receiver Shutdown Packet The contents of this section apply to the FLEX™ Roaming Decoder. They are not applicable to the FLEX™ Non-Roaming Decoder. 1. Calculating Time Left The receiver shutdown packet gives timing information to the host.
Page 397 2. Calculating How Long Tasks Take Since the TimeToTaskDisabled discussed in the previous section limits how much the host can do while the FLEX decoder is battery saving, it is necessary for the host to know how long it can take the FLEX decoder to perform a task.
Page 398 TotalWarmUpTime: The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets. AST: The value configured using the timing control packet.
Page 399: Timing Diagrams (Reference Data)
12.6 Timing Diagrams (Reference Data) The following diagrams show the timing in a standalone FLEX™ Decoder IC. They do not apply to this LSI, and should be used only for reference. 12.6.1 SPI Timing The following diagram and table describe the timing specifications of the SPI interface. READY LEAD2 LAG2...
Page 400 Table 12-34 SPI Timing (VDD = 1.8 V to 3.6 V, TA = -20ºC to 75ºC) Characteristic Conditions Symbol Min* Max* Unit Operating Frequency Cycle Time 1000 Select Lead Time LEAD1 De-select Lag Time LAG1 µs Select-to-Ready Time previous packet did not program an address word* =50pf µs...
Page 401: Start-Up Timing
12.6.2 Start-up Timing The following diagram and table describe the timing specifications of the FLEX decoder when power is applied. START Oscillator RESET RESET READY RHRL Figure 12-14 Start-up Timing Table 12-35 Start-up Timing (V = 1.8 V to 3.6 V, T = -20ºC to 75ºC) Characteristic Conditions...
Page 402: Reset Timing
12.6.3 Reset Timing The following diagram and table describe the timing specifications of the FLEX decoder when it is reset. RESET READY RLRH RHRL Figure 12-15 Reset Timing Table 12-36 Reset Timing (V = 1.8 V to 3.6 V, T = -20ºC to 75ºC) Characteristic Conditions...
Page 403: Section 13 Electrical Characteristics
Section 13 Electrical Characteristics 13.1 Absolute Maximum Ratings Table 13-1 lists the absolute maximum ratings. Table 13-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Programming voltage –0.3 to +13.0 Input voltage Ports other than Port B –0.3 to V...
Page 404: Electrical Characteristics
Electrical Characteristics 13.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8/3937 Series and H8/3937R Series are indicated by the shaded region in the figures. 1. Power supply voltage and oscillator frequency range 10.0...
Page 405 2. Power supply voltage and operating frequency range 19.2 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) • Subactive mode • Subsleep mode (except CPU) • Watch mode (except CPU) 15.625 • Active (medium-speed) mode (except A/D converter) •...
Page 406: Dc Characteristics
13.2.2 DC Characteristics Table 13-2 lists the DC characteristics of the H8/3937 Series and H8/3937R Series. Table 13-2 DC Characteristics = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V, Ta = –20°C to +75°C (including subactive mode) unless otherwise indicated.
Page 407 Values Item Symbol Applicable Pins Unit Test Condition Notes Output to P1 , P3 to P3 – 0.3 — — –I = 0.1 mA high to P4 , P5 to P5 voltage to P6 , P7 to P7 to P8 , P9 to P9 to PA...
Page 408 Values Item Symbol Applicable Pins Unit Test Condition Notes Active — — Active (high- speed) OPE1 mode mode current = 3 V, Refer- dissi- = 2 MHz ence value pation — 0.25 — Active (medium- OPE2 speed) mode = 3 V, Refer- = 2 MHz, ence...
Page 409 Values Item Symbol Applicable Pins Unit Test Condition Notes Allow- I CLKOUT — — able All output pins except — — output CLKOUT current (per pin) ∑ Allow- All output pins — — 20.0 able output current (total) Allow- –I CLKOUT —...
Page 410: Ac Characteristics
13.2.3 AC Characteristics Table 13-3 lists the control signal timing, and tables 13-4 list the serial interface timing of the H8/3937 Series and 3937R Series. Table 13-3 Control Signal Timing = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V, Ta = –20°C to +75°C...
Page 411 Applicable Values Reference Item Symbol Pins Unit Test Condition Figure External clock — — = 2.7 V to 3.6 V Figure 13-1 rise time — — = 1.8 V to 3.6 V — — 55.0 Figure 13-1 External clock — —...
Page 412 Table 13-4 Serial Interface (SCI31, SCI32) Timing = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V, Ta = –20°C to +75°C (including subactive mode) unless otherwise indicated. Values Reference Item Symbol Min Unit Test Conditions...
Page 413: A/D Converter Characteristics
13.2.4 A/D Converter Characteristics Table 13-5 shows the A/D converter characteristics of the H8/3937 Series and H8/3937R Series. Table 13-5 A/D Converter Characteristics = 1.8 V to 3.6 V, V = AV = 0.0 V, Ta = –20°C to +75°C (including subactive mode) unless otherwise indicated.
Page 414: Operation Timing
13.3 Operation Timing Figures 13-1 to 13-7 show timing diagrams. , tw OSC1 Figure 13-1 Clock Input Timing Figure 13-2 RES Low Width to IRQ to WKP ADTRG, TMIC, TMIF, TMIG Figure 13-3 Input Timing...
Page 415 Figure 13-4 UD Pin Minimum Modulation Width Timing SCKW scyc Figure 13-5 SCK3 Input Clock Timing...
Page 416 scyc or V or V (transmit data) (receive data) Note: * Output timing reference levels Output high = 1/2 V + 0.2 V Output low = 0.8 V Load conditions are shown in figure 13-7. Figure 13-6 SCI3 Synchronous Mode Input/Output Timing...
Page 417: Output Load Circuit
13.4 Output Load Circuit 2.4 kΩ Output pin 12 k Ω 30 pF Figure 13-7 Output Load Condition 13.5 Resonator Equivalent Circuit Crystal Resonator Parameter Ceramic Resonator Parameters Frequency (MHz) 4.193 Frequency (MHz) 100 Ω 8.8 Ω (max) (max) (max) 16 pF (max) 36 pF...
Page 418: Usage Note
13.6 Usage Note The ZTAT and mask ROM versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on.
Page 419: Appendix A Cpu Instruction Set
Appendix A CPU Instruction Set Instructions Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter...
Page 420 Table A-1 lists the H8/300L CPU instruction set. Table A-1 Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C — — ↑ ↓ ↑ ↓ 0 — 2 B #xx:8 → Rd8 MOV.B #xx:8, Rd —...
Page 421 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C — ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ 2 B Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ 2 B Rd8+Rs8 →...
Page 422 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C — — ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ 2 SHAL.B Rd — — ↑ ↓ ↑ ↓ 0 ↑ ↓ 2 SHAR.B Rd — — ↑ ↓ ↑ ↓ 0 ↑ ↓ 2 SHLL.B Rd —...
Page 423 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C B (Rn8 of @Rd16) ← 0 BCLR Rn, @Rd — — — — — — 8 B (Rn8 of @aa:8) ← 0 BCLR Rn, @aa:8 — — — — — — 8 B (#xx:3 of Rd8) ←...
Page 424 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C — — — — — ↑ ↓ 2 B C∧(#xx:3 of Rd8) → C BIAND #xx:3, Rd — — — — — ↑ ↓ 6 B C∧(#xx:3 of @Rd16) → C BIAND #xx:3, @Rd —...
Page 425 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation H N Z V C — PC ← Rn16 JMP @Rn — — — — — — 4 — PC ← aa:16 JMP @aa:16 — — — — — — 6 —...
Page 426 Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) Set to 1 if decimal adjustment produces a carry;...
Page 427: Operation Code Map
Operation Code Map Table A-2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Page 428 Table A-2 Operation Code Map...
Page 429: Number Of Execution States
Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A-4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table A-3 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I ×...
Page 430 Table A-4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd...
Page 431 Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST...
Page 432 Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 CMP.
Page 433 Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic MOV.B Rs, @(d:16, MOV.B Rs, @–Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd MOV.W @(d:16, Rs), MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd...
Page 434 Instruction Branch Stack Byte Data Word Data Internal Instruc- Fetch Addr. Read Operation Access Access Operation tion Mnemonic SUB.B Rs, Rd SUB.W Rs, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd SUBS.W #2, Rd POP Rd PUSH PUSH Rs SUBX SUBX.B #xx:8, Rd...
Page 435: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Addresses Lower Register Bit Names Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'90 WEGR WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 System control H'91 SPCR...
Page 436 Lower Register Bit Names Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'B2 TCSRW B6WI TCWE B4WI TCSRWE B2WI WDON BOW1 WRST Watchdog H'B3 TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1...
Page 437 Lower Register Bit Names Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'D9 PDR6 I/O Port H'DA PDR7 H'DB PDR8 H'DC PDR9 — — — — H'DD PDRA —...
Page 438: Functions
Functions Register Register Address to which the Name of acronym name register is mapped on-chip supporting module TMC—Timer mode register C H'B4 Timer C numbers Initial bit TMC7 TMC6 TMC5 — — TMC2 TMC1 TMC0 values Initial value Names of the bits.
Page 439 WEGR—Wakeup Edge Select Register H'90 System control WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value Read/Write WKPn edge selected WKPn pin falling edge detected WKPn pin rising edge detected (n = 0 to 7) SPCR—Serial Port Control Register H'91 —...
Page 440 CWOSR—Subclock Output Select Register H'92 Timer A — — — — — — — CWOS Initial value Read/Write — — — — — — — TMOW pin clock select Clock output from TMA is output ø is output...
Page 441 SMR31—Serial mode register 31 H'98 SCI31 COM31 CHR31 PE31 PM31 STOP31 MP31 CKS311 CKS310 Initial value Read/Write Clock select ø clock øw/2 clock/øw clock ø/16 clock ø/64 clock Multiprocessor mode Multiprocessor communication function disabled Multiprocessor communication function enabled Stop bit length 1 stop bit 2 stop bits Parity mode...
Page 442 BRR31—Bit rate register31 H'99 SCI31 BRR317 BRR316 BRR315 BRR314 BRR313 BRR312 BRR311 BRR310 Initial value Read/Write Serial transmit/receive bit rate setting...
Page 443 SCR31—Serial control register 31 H'9A SCI31 TIE31 RIE31 TE31 RE31 MPIE31 TEIE31 CKE311 CKE310 Initial value Read/Write Clock enable Description Bit 1 Bit 0 CKE311 CKE310 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous Internal clock...
Page 444 TDR31—Transmit data register 31 H'9B SCI31 TDR317 TDR316 TDR315 TDR314 TDR313 TDR312 TDR311 TDR310 Initial value Read/Write Data for transfer to TSR...
Page 445 SSR31—Serial status register31 H'9C SCI3 TDRE31 RDRF31 OER31 FER31 PER31 TEND31 MPBR31 MPBT31 Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmit end Transmission in progress...
Page 446 RDR31—Receive data register 31 H'F9D SCI31 RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310 Initial value Read/Write Serial receive data...
Page 447 SCR1—Serial control register 1 H'A0 SCI1 SNC1 SNC0 MRKON LTCH CKS3 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 Serial Clock Cycle Prescaler Bit 2 Bit 1 Bit 0 Clock Cycle Division CKS2 CKS1 CKS0 Ratio ø = 2.5 MHz 409.6 µs ø/1024 102.4 µs...
Page 448 SCSR1—Serial control status register 1 H'A1 SCI1 — ORER — — — MTRF Initial value Read/Write — R/(W) — — — Start flag Read Transfer operation stopped Write Invalid Read Transfer operation in progress Write Starts transfer operation Tail mark transmission flag 0 Idle state, or 8-bit/16-bit data transfer in progress 1 Tail mark transmission in progress Overrun error flag...
Page 449 SDRU—Serial data register U H'A2 SCI1 SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Used for transmit data setting and receive data storage 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data register SDRL—Serial data register L H'A3 SCI1...
Page 450 SMR32—Serial mode register 32 H'A8 SCI32 COM32 CHR32 PE32 PM32 STOP32 MP32 CKS321 CKS320 Initial value Read/Write Clock select ø clock øw/2 clock/øw clock ø/16 clock ø/64 clock Multiprocessor mode Multiprocessor communication function disabled Multiprocessor communication function enabled Stop bit length 1 stop bit 2 stop bits Parity mode...
Page 451 BRR32—Bit rate register 32 H'A9 SCI32 BRR327 BRR326 BRR325 BRR324 BRR323 BRR322 BRR321 BRR3120 Initial value Read/Write Serial transmit/receive bit rate setting...
Page 452 SCR32—Serial control register 32 H'AA SCI32 TIE32 RIE32 TE32 RE32 MPIE32 TEIE32 CKE321 CKE320 Initial value Read/Write Clock enable Description Bit 1 Bit 0 CKE321 CKE320 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous Internal clock...
Page 453 TDR32—Transmit data register 32 H'AB SCI32 TDR327 TDR326 TDR325 TDR324 TDR323 TDR322 TDR321 TDR320 Initial value Read/Write Data for transfer to TSR...
Page 454 SSR32—Serial status register 32 H'AC SCI32 TDRE32 RDRF32 OER32 FER32 PER32 TEND32 MPBR32 MPBT32 Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmit end...
Page 455 RDR32—Receive data register 32 H'AD SCI32 RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320 Initial value Read/Write Serial receive data TMA—Timer mode register A H'B0 Timer A TMA7 TMA6 TMA5 — TMA3 TMA2 TMA1 TMA0 Initial value Read/Write — Clock output select* Internal clock select ø/32 Prescaler and Divider Ratio...
Page 456 TCA—Timer counter A H'B1 Timer A TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write Count value...
Page 457 TCSRW—Timer control/status register W H'B2 Watchdog timer B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST Initial value Read/Write R/(W) R/(W) R/(W) R/(W) Watchdog timer reset 0 [Clearing conditions] • Reset by RES pin • When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 [Setting condition] When TCW overflows and a reset signal is generated Bit 0 write inhibit...
Page 458 TCW—Timer counter W H'B3 Watchdog timer TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write Count value TMC—Timer mode register C H'B4 Timer C TMC7 TMC6 TMC5 — — TMC2 TMC1 TMC0 Initial value Read/Write — — Clock select Internal clock: ø/8192 Internal clock:...
Page 459 TCC—Timer counter C H'B5 Timer C TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write Count value TLC—Timer load register C H'B5 Timer C TLC7 TLC6 TLC5 TLC4 TLC3 TLC2 TLC1 TLC0 Initial value Read/Write Reload value Note: TLC is allocated to the same address as TCC. In a write, the value is written to TLC.
Page 460 TCRF—Timer control register F H'B6 Timer F TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value Read/Write Clock select L Counting on external event (TMIF) rising/falling edge Not available Internal clock ø/32 Internal clock ø/16 Internal clock ø/4 Internal clock øw/4 * Don’t care Toggle output level L Low level...
Page 461 TCSRF—Timer control/status register F H'B7 Timer F OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Counter clear L TCFL clearing by compare match is disabled TCFL clearing by compare match is enabled Timer overflow interrupt enable L TCFL overflow interrupt request is disabled TCFL overflow interrupt request is enabled...
Page 462 TCFH—8-bit timer counter FH H'B8 Timer F TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 Initial value Read/Write Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF). TCFL—8-bit timer counter FL H'B9 Timer F...
Page 463 OCRFL—Output compare register FL H'BB Timer F OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Initial value Read/Write Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF).
Page 464 TMG—Timer mode register G H'BC Timer G OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value Read/Write R/(W)* R/(W)* Clock select Internal clock: counting on ø/64 Internal clock: counting on ø/32 Internal clock: counting on ø/2 Internal clock: counting on øw/4 Counter clear TCG clearing is disabled TCG cleared by falling edge of input capture input signal...
Page 465 ICRGF—Input capture register GF H'BD Timer G ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write Store TCG value at falling edge of input capture signal ICRGR—Input capture register GR H'BE Timer G ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0...
Page 466 AMR—A/D mode register H'C6 A/D converter TRGE — — Initial value Read/Write — — Channel select Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected Reserved * Don’t care External trigger select 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select...
Page 467 ADRRH—A/D result register H H'C4 A/D converter ADRRL—A/D result register L H'C5 ADRRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write A/D conversion result ADRRL ADR1 ADR0 — — —...
Page 468 PMR1—Port mode register 1 H'C8 I/O port IRQ3 IRQ2 IRQ1 IRQ4 TMIG TMOFH TMOFL TMOW Initial value Read/Write /TMOW pin function switch Functions as P1 I/O pin 1 Functions as TMOW output pin /TMOFL pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOFL output pin /TMOFH pin function switch...
Page 469 PMR2—Port mode register 2 H'C9 I/O port — — POF1 — — SCK1 Initial value Read/Write — — — — /SCK function switch 0 Functions as P2 Functions as SCK function switch 0 Functions as P2 Functions as SI input function switch 0 Functions as P2 Functions as SO...
Page 470 PMR3—Port mode register 3 H'CA I/O port — — WDCKS IRQ0 RESO — Initial value Read/Write — — — /UD pin function switch 0 Functions as P3 I/O pin 1 Functions as UD input pin /RESO pin function switch 0 Functions as P3 I/O pin 1 Functions as RESO I/O pin /IRQ0 pin function switch...
Page 471 PMR5—Port mode register 5 H'CC I/O port Initial value Read/Write /WKP pin function switch 0 Functions as P5 I/O pin 1 Functions as WKP input pin (n = 7 to 0) PDR1—Port data register 1 H'D4 I/O ports Initial value Read/Write Data for port 1 pins PDR2—Port data register 2...
Page 472 PDR3—Port data register 3 H'D6 I/O ports Initial value Read/Write Data for port 3 pins PDR4—Port data register 4 H'D7 I/O ports — — — — Initial value Read/Write — — — — Reads P4 state Data for port pins P4 to P4 PDR5—Port data register 5 H'D8...
Page 473 PDR6—Port data register 6 H'D9 I/O ports Initial value Read/Write Data for port 6 pins PDR7—Port data register 7 H'DA I/O ports Initial value Read/Write Data for port 7 pins PDR8—Port data register 8 H'DB I/O ports Initial value Read/Write Data for port 8 pins...
Page 474 PDR9—Port data register 9 H'DC I/O ports — — — — Initial value Read/Write — — — — Data for port 9 pins PDRA—Port data register A H'DD I/O ports — — — — Initial value Read/Write — — — —...
Page 475 PUCR1—Port pull-up control register 1 H'E0 I/O ports PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 Initial value Read/Write Port 1 input pull-up MOS control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR1 specification is 0 (input port specification) PUCR3—Port pull-up control register 3 H'E1...
Page 476 PUCR5—Port pull-up control register 5 H'E2 I/O ports PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 Initial value Read/Write Port 5 input pull-up MOS control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR5 specification is 0 (input port specification) PUCR6—Port pull-up control register 6 H'E3...
Page 477 PCR2—Port control register 2 H'E5 I/O ports — — — PCR2 PCR2 PCR2 PCR2 PCR2 Initial value Read/Write — — — Port 2 input/output select Input pin 1 Output pin PCR3—Port control register 3 H'E6 I/O ports PCR3 PCR3 PCR3 PCR3 PCR3 PCR3...
Page 478 PCR5—Port control register 5 H'E8 I/O ports PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 Initial value Read/Write Port 5 input/output select 0 Input pin 1 Output pin PCR6—Port control register 6 H'E9 I/O ports PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6...
Page 479 PCR8—Port control register 8 H'EB I/O ports PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 Initial value Read/Write Port 8 input/output select 0 Input pin 1 Output pin PCR9—Port control register 9 H'EC I/O ports — — — — PCR9 PCR9 PCR9 PCR9...
Page 480 SYSCR1—System control register 1 H'F0 System control SSBY STS2 STS1 STS0 LSON — Initial value Read/Write — Active (medium-speed) mode clock select ø ø ø ø /128 Low speed on flag 0 The CPU operates on the system clock (ø) 1 The CPU operates on the subclock (ø...
Page 481 SYSCR2—System control register 2 H'F1 System control — — — NESEL DTON MSON Initial value Read/Write — — — Subactive mode clock select ø /8 ø /4 ø /2 Medium speed on flag *: Don’t care 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct transfer on flag 0 •...
Page 482 IEGR—IRQ edge select register H'F2 System control — — — IEG4 IEG3 IEG2 IEG1 IEG0 Initial value Read/Write — — — edge select 0 Falling edge of IRQ signal input is detected Rising edge of IRQ signal input is detected edge select 0 Falling edge of IRQ , TMIC pin input is detected...
Page 483 IENR1—Interrupt enable register 1 H'F3 System control IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write to IRQ interrupt enable 0 Disables IRQ to IRQ interrupt requests Enables IRQ to IRQ interrupt requests Note: IRQ is an internal signal that performs interfacing to the FLEX™...
Page 484 IENR2—Interrupt enable register 2 H'F4 System control IENDT IENAD — IENTG IENTFH IENTFL IENTC — Initial value Read/Write — Timer C interrupt enable Disables timer C interrupt requests Enables timer C interrupt requests Timer FL interrupt enable 0 Disables timer FL interrupt requests 1 Enables timer FL interrupt requests Timer FH interrupt enable 0 Disables timer FH interrupt requests...
Page 485 IRR1—Interrupt request register 1 H'F6 System control IRRTA IRRS1 — IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write — IRQ4 to IRQ0 interrupt request flags 0 Clearing conditions: When IRRIn = 1, it is cleared by writing 0 1 Setting conditions: When pin IRQn is designated for interrupt...
Page 486 IRR2—Interrupt request register 2 H'F7 System control IRRDT IRRAD — IRRTG IRRTFH IRRTFL IRRTC — Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* — Timer C interrupt request flag 0 Clearing conditions: When IRRTC = 1, it is cleared by writing 0 1 Setting conditions: When the timer C counter value overflows (from H'FF to H'00) or underflows (from H'00 to H'FF)
Page 487 IWPR—Wakeup interrupt request register H'F9 System control IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Wakeup interrupt request register 0 Clearing conditions: When IWPFn = 1, it is cleared by writing 0 1 Setting conditions: When pin WKPn is designated for wakeup input and a rising or falling edge is input at that pin...
Page 488 CKSTPR1—Clock stop register 1 H'FA System control S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write Timer A module standby mode control 0 Timer A is set to module standby mode Timer A module standby mode is cleared Timer C module standby mode control 0 Timer C is set to module standby mode Timer C module standby mode is cleared...
Page 489 CKSTPR2—Clock stop register 2 H'FB System control — — — — — — — WDCKSTP Initial value Read/Write — — — — — — — WDT module standby mode control 0 WDT is set to module standby mode WDT module standby mode is cleared...
Page 490: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Block Diagrams of Port 1 (low level during reset and in standby mode) PUCR1 PMR1 PDR1 PCR1 n–4 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n = 7 to 4 Figure C-1 (a) Port 1 Block Diagram (Pins P1...
Page 491 PUCR1 PMR1 PDR1 PCR1 Timer G module TMIG PDR1 : Port data register 1 PCR1 : Port control register 1 PMR1 : Port mode register 1 PUCR1 : Port pull-up control register 1 Figure C-1 (b) Port 1 Block Diagram (Pin P1...
Page 492 Timer F module TMOFH (P1 TMOFL (P1 PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n= 2 or 1 Figure C-1 (c) Port 1 Block Diagram (Pins P1 and P1...
Page 493 øw Timer A module TMOW CWOS PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C-1 (d) Port 1 Block Diagram (Pin P1...
Page 494: Block Diagrams Of Port 2 [Chip Internal I/O Port]
Block Diagrams of Port 2 [Chip Internal I/O Port] RES (Low in reset) FLEX Decoder RESET PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 Figure C-2 (a) Port 2 Block Diagram (Pin P2 FLEX Decoder PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2...
Page 495 SCI1 module PMR2 FLEX Decoder MOSI PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 Figure C-2 (c) Port 2 Block Diagram (Pin P2...
Page 496 PMR2 FLEX Decoder MISO PDR2 PCR2 SCI1 module PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 Figure C-2 (d) Port 2 Block Diagram (Pin P2...
Page 497 SCI1 module EXCK PMR2 FLEX Decoder PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 Figure C-2 (e) Port 2 Block Diagram (Pin P2...
Page 498: Block Diagrams Of Port 3
Block Diagrams of Port 3 PUCR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n=7 or 6 Figure C-3 (a) Port 3 Block Diagram (Pins P3 and P3...
Page 499 PUCR3 SCINV1 SCI31 module TE31 TXD31 PDR3 PCR3 PDR3 : Port data register 3 PCR3 : Port control register 3 PUCR3 : Port pull-up control register 3 SCINV1 : Bit 1 of serial port control register (SPCR) Figure C.3 (b) Port 3 Block Diagram (Pin P3...
Page 500 PUCR3 SCI31 module RE31 RXD31 PDR3 PCR3 SCINV0 PDR3 : Port data register 3 PCR3 : Port control register 3 PUCR3 : Port pull-up control register 3 SCINV0 : Bit 0 of serial port control register (SPCR) Figure C.3 (c) Port 3 Block Diagram (Pin P3...
Page 501 PUCR3 SCI31 module SCKIE31 SCKOE31 SCKO31 SCKI31 PDR3 PCR3 PDR3 : Port data register 3 PCR3 : Port control register 3 PUCR3 : Port pull-up control register 3 Figure C.3 (d) Port 3 Block Diagram (Pin P3...
Page 502 RESO PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (e) Port 3 Block Diagram (Pin P3...
Page 503 PUCR3 PMR3 PDR3 PCR3 Timer C module PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C-3 (f) Port 3 Block Diagram (Pin P3...
Page 504 PUCR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 Figure C-3 (g) Port 3 Block Diagram (Pin P3...
Page 505: Block Diagrams Of Port 4
Block Diagrams of Port 4 PMR4 FLEX Decoder READY PMR4: Port mode register 4 Figure C.4 (a) Port 4 Block Diagram (Pin P4 ) [Chip Internal Input Port]...
Page 506 SCINV3 SCI32 module TE32 TXD32 PDR4 PCR4 PDR4 : Port data register 4 PCR4 : Port control register 4 SCINV3 : Bit 3 of serial port control register (SPCR) Figure C.4 (b) Port 4 Block Diagram (Pin P4...
Page 507 SCI32 module RE32 RXD32 PDR4 PCR4 SCINV2 PDR4 : Port data register 4 PCR4 : Port control register 4 SCINV2 : Bit 2 of serial port control register (SPCR) Figure C.4 (c) Port 4 Block Diagram (Pin P4...
Page 508 SCI32 module SCKIE32 SCKOE32 SCKO32 SCKI32 PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (d) Port 4 Block Diagram (Pin P4...
Page 509: Block Diagram Of Port 5
Block Diagram of Port 5 PUCR5 PMR5 PDR5 PCR5 PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 n = 7 to 0 Figure C.5 Port 5 Block Diagram...
Page 510: Block Diagram Of Port 6
Block Diagram of Port 6 PUCR6 PDR6 PCR6 PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure C.6 Port 6 Block Diagram...
Page 511: Block Diagram Of Port 7
Block Diagram of Port 7 PDR7 PCR7 PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure C.7 Port 7 Block Diagram...
Page 512: Block Diagrams Of Port 8
Block Diagrams of Port 8 PDR8 PCR8 PDR8: Port data register 8 PCR8: Port control register 8 n= 7 to 0 Figure C-8 Port 8 Block Diagram...
Page 513: Block Diagram Of Port 9
Block Diagram of Port 9 PDR9 PCR9 PDR9: Port data register 9 PCR9: Port control register 9 n = 3 to 0 Figure C-9 Port 9 Block Diagram...
Page 514: Block Diagram Of Port A
C.10 Block Diagram of Port A PDRA PCRA PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure C.10 Port A Block Diagram...
Page 515: Block Diagram Of Port B
C.11 Block Diagram of Port B Internal data bus A/D module AMR3 to AMR0 n = 7 to 0 Figure C-11 Port B Block Diagram...
Page 516: Appendix D Port States In The Different Processing States
Appendix D Port States in the Different Processing States Table D-1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active to P1 High- Retained Retained High- Retained Functions Functions impedance impedance* Retained Retained Retained Retained Functions Functions High to P2 to P3 High-...
Page 517: Appendix E List Of Product Codes
Appendix E List of Product Codes Table E.1 Product Code Lineup Package (Hitachi Package Code) Product Type Product Code Mark Code H8/3937 H8/3935 Mask ROM HD6433935X HD6433935(***)X 100-pin TQFP (TFP-100B) Series versions HD6433935W HD6433935(***)W 100-pin TQFP (TFP-100G) H8/3936 Mask ROM...
Page 518: Appendix F Package Dimensions
Appendix F Package Dimensions Dimensional drawings of the H8/3937 Series and H8/3937R Series packages TFP-100B and TFP- 100G are shown in following figures F-1 and F-2, respectively. Unit: mm 16.0 ± 0.2 *0.22 ± 0.05 0.08 0.20 ± 0.04 0° – 8°...
Page 519 Unit: mm 14.0 ± 0.2 *0.18 ± 0.05 0.07 0.16 ± 0.04 0° – 8° 0.5 ± 0.1 0.10 Hitachi Code TFP-100G JEDEC — EIAJ Conforms *Dimension including the plating thickness Base material dimension Weight (reference value) 0.4 g Figure F-2 TFP-100G Package Dimensions...
Page 521 Publication Date: 1st Edition, February 2001 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.

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H8/3937r seriesH8/3937H8/3936 H8/3935H8/3937rH8/3936r ... Show all

Hitachi H8/3937 Series Hardware Manual

Overview

Cpu

Exception Handling

Clock Pulse Generators

Power-Down Modes

Rom

Ram

I/O Ports

Timers

Section 10 Serial Communication Interface

Section 11 A/D Converter

Section 12 FLEX Roaming Decoder

Section 13 Electrical Characteristics

Appendix A CPU Instruction Set

Quick Links

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Summary of Contents for Hitachi H8/3937 Series