Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 557

Table 11.17 TIORL_3
Bit 7 Bit 6 Bit 5
IOD3 IOD2 IOD1
0 0 0
1
1 0
1
1 0 0
1
1 x
Legend: x: Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and ø/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Description
Bit 4 TGRD_3
IOD0 Function
0 Output
compare
1
2
register*
0
1
0
1
0
1
0 Input
capture
2
register*
1
x
x
TIOCD3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Capture input source is TIOCD3 pin
Input capture at rising edge
Capture input source is TIOCD3 pin
Input capture at falling edge
Capture input source is TIOCD3 pin
Input capture at both edges
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down*
Rev. 1.0, 09/01, page 513 of 904
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