Usage Notes; Exdmac Register Access During Operation; Module Stop State; Edreq Pin Falling Edge Activation - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

8.6

Usage Notes

8.6.1

EXDMAC Register Access during Operation

Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in
operation (including the transfer standby state). Transfer must be disabled before changing a
setting for an operational channel.
8.6.2

Module Stop State

When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC
enters the module stop state. However, 1 cannot be written to the MSTP14 bit when any of the
EXDMAC's channels is enabled for transfer, or when an interrupt is being requested. Before
setting the MSTP14 bit, first clear the EDA bit in EDMDR to 0, then clear the IRF or EDIE bit in
EDMDR to 0.
When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following
EXDMAC register settings remain valid in the module stop state, and so should be changed, if
necessary, before making the module stop transition.
• ETENDE = 1 in EDMDR ((7(1' pin enable)
• EDRAKE = 1 in EDMDR (('5$. pin enable)
• AMS = 1 in EDMDR (('$&. pin enable)
('5(4 ('5(4 Pin Falling Edge Activation ('5(4 ('5(4
8.6.3
Falling edge sensing on the ('5(4 pin is performed in synchronization with EXDMAC internal
operations, as indicated below.
[1] Activation request standby state: Waits for low level sensing on ('5(4 pin, then goes to [2].
[2] Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3].
[3] Activation request disabled state: Waits for high level sensing on ('5(4 pin, then goes to [1].
After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used
for the initial activation after transfer is enabled.
8.6.4

Activation Source Acceptance

At the start of activation source acceptance, low level sensing is used for both falling edge sensing
and low level sensing on the ('5(4 pin. Therefore, a request is accepted in the case of a low
level at the ('5(4 pin that occurs before execution of the EDMDR write for setting the transfer-
enabled state.
Rev. 1.0, 09/01, page 376 of 904