Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 824

Table 20.5 Boot Mode Operation
Host Operation
Processing Contents
Continuously transmits data H'00
at specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
H'AA reception
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte)
Transmits 1-byte of programming
control program (repeated for N times)
H'AA reception.
Table 20.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate
19,200 bps
9,600 bps
4,800 bps
Rev. 1.0, 09/01, page 780 of 904
Communication Contents
H'00, H'00 . . . H'00
Upper bytes, lower bytes
Boot program
erase error
System Clock Frequency Range of LSI
20 MHz
8 to 20 MHz
4 to 20 MHz
Branches to boot program at reset-start.
• Measures low-level period of receive data H'00.
• Calculates bit rate and sets BRR in SCI_1.
• Transmits data H'00 to host as adjustment end
H'00
indication.
H'55
H'AA Transmits data H'AA to host when data H'55 is
received.
Echobacks the 2-byte data
Echoback
received to host.
Echobacks received data to host and also
H'XX
transfers it to RAM.
Echoback
(repeated for N times)
H'FF
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'AA
H'FF to host and aborts operation.)
Branches to programming control program
transferred to on-chip RAM and starts
execution.
LSI Operation
Processing Contents
Boot program initiation