Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 418

Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant
channel, and can be sent to the interrupt controller independently. The relative priority order of the
channels is determined by the interrupt controller (see table 8.4).
Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever
the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR.
IRF bit
Transfer end interrupt
EDIE bit
Figure 8.45 Transfer End Interrupt Logic
Interrupt source settings are made individually with the interrupt enable bits in the registers for the
relevant channels. The transfer counter's transfer end interrupt is enabled or disabled by means of
the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of
the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by
means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding
interrupt enable bit is set to 1, the IRF bit in EDMDR is set to 1. The IRF bit is set by all interrupt
sources indiscriminately.
The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the
interrupt handling routine, or by re-setting the transfer counter and address registers and then
setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of
the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46.
Rev. 1.0, 09/01, page 374 of 904