Mode Setting With Cascaded Connection; Interrupts In Module Stop Mode - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Timing of Switchover
by Means of CKS1
No. and CKS0 Bits
4 Switching from high
to high
Notes: 1. Includes switching from low to stop, and from stop to low.
2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
13.8.6

Mode Setting with Cascaded Connection

If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
and compare match count modes simultaneously.
13.8.7

Interrupts in Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC and DMAC activation source. Interrupts should
therefore be disabled before entering module stop mode.
TCNT Clock Operation
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT N N+1 N+2
CKS bit write
Rev. 1.0, 09/01, page 611 of 904