Cas Latency Control - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

6.7.7

CAS Latency Control

CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency
count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the
CAS latency control cycle (T
AST2 bit of ASTCR. Figure 6.45 shows the CAS latency control timing when synchronous
DRAM of CAS latency 3 is connected.
The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of
synchronous DRAM to be connected.
Table 6.10 Setting CAS Latency
W22 W21 W20
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Rev. 1.0, 09/01, page 186 of 904
) is inserted. WTCRB can be set regardless of the setting of the
c1
Description
Connect synchronous DRAM of
CAS latency 1
Connect synchronous DRAM of
CAS latency 2
Connect synchronous DRAM of
CAS latency 3
Connect synchronous DRAM of
CAS latency 4
Reserved (must not used)
Reserved (must not used)
Reserved (must not used)
Reserved (must not used)
CAS Latency Control Cycle
Inserted
0 state
1 state
2 states
3 states
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