Input/Output Pins; Register Descriptions - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

8.2

Input/Output Pins

Table 8.1 summarizes the pins of the EXDMAC.
Table 8.1 Pin Configuration
Channel Name
2 EXDMA transfer request 2
EXDMA transfer
acknowledge 2
EXDMA transfer end 2
('5(45 acceptance
acknowledge
3 EXDMA transfer request 3
EXDMA transfer
acknowledge 3
EXDMA transfer end 3
('5(46 acceptance
acknowledge
8.3

Register Descriptions

The EXDMAC has the following registers.
• EXDMA source address register_2 (EDSAR_2)
• EXDMA destination address register_2 (EDDAR_2)
• EXDMA transfer count register_2 (EDTCR_2)
• EXDMA mode control register_2 (EDMDR_2)
• EXDMA address control register_2 (EDACR_2)
• EXDMA source address register_3 (EDSAR_3)
• EXDMA destination address register_3 (EDDAR_3)
• EXDMA transfer count register_3 (EDTCR_3)
• EXDMA mode control register_3 (EDMDR_3)
• EXDMA address control register_3 (EDACR_3)
Abbre-
viation I/O
('5(45
Input
('$&.5
Output
(7(1'5
Output
('5$.5
Output
('5(46
Input
('$&.6
Output
(7(1'6
Output
('5$.6
Output
Function
Channel 2 external request
Channel 2 single address transfer
acknowledge
Channel 2 transfer end
Notification to external device of
channel 2 external request
acceptance and start of transfer
processing
Channel 3 external request
Channel 3 single address transfer
acknowledge
Channel 3 transfer end
Notification to external device of
channel 3 external request
acceptance and start of transfer
processing
Rev. 1.0, 09/01, page 319 of 904