Module Stop Mode - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the 67%<
pin and the 5(6 pin. When the 67%< pin is driven high while the 5(6 pin is low, the reset state is
set and clock oscillation is started. Ensure that the 5(6 pin is held low until the clock oscillator
stabilizes (for details on the oscillation stabilization time, refer to table 22.2). When the 5(6 pin is
subsequently driven high, a transition is made to the program execution state via the reset
exception handling state.
Hardware Standby Mode Timing: Figure 22.3 shows an example of hardware standby mode
timing.
When the 67%< pin is driven low after the 5(6 pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the 67%< pin high,
waiting for the oscillation stabilization time, then changing the 5(6 pin from low to high.
Oscillator
Oscillation Reset
stabilization exception
time handling
Figure 22.3 Hardware Standby Mode Timing
22.2.5

Module Stop Mode

Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI are retained.
After reset clearance, all modules other than the EXDMAC, DMAC, and DTC are in module stop
mode.
Rev. 1.0, 09/01, page 812 of 904