Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 348

ø
Address bus
DMA control Idle
Channel
[1] Acceptance after transfer enabling; the
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle;
[4] [7] When the
cycle is completed. (As in [1], the
the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.30 Example of '5(4
'5(4 pin sampling is performed every cycle, with the rising edge of the next ø cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the '5(4 pin low level is sampled while acceptance by means of the '5(4 pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and '5(4 pin high level sampling for edge detection is started. If '5(4 pin
high level sampling has been completed by the time the DMA single cycle ends, acceptance
resumes after the end of the single cycle, '5(4 pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
'5(4 Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel '5(4
'5(4 '5(4
for which the '5(4 pin is selected.
Rev. 1.0, 09/01, page 304 of 904
Bus release DMA single
Transfer source/
destination
Single
Request clear
Request
period
Minimum of
2 cycles
[1] [2] [3]
Acceptance resumes
pin high level sampling on the rising edge of ø starts.
pin high level has been sampled, acceptance is resumed after the single
'5(4 Pin Falling Edge Activated Single Address Mode Transfer
'5(4 '5(4
Bus release
Idle Single
Request
Minimum of
2 cycles
[4] [5] [6]
pin low level is sampled on the rising edge of ø,
pin low level is sampled on the rising edge of ø, and
DMA single Bus release
Transfer source/
destination
Idle
Request clear
period
[7]
Acceptance resumes