Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 55

Type Symbol
Address bus A23 to A0 31 to 26,
Data bus D15 to
D0
Bus control CS7 to
CS0
A S
RD
H W R
LW R
BREQ
BREQ O
BA CK
U CA S
LCA S
D Q M U
D Q M L
Pin No. I/O
Output These pins output an address.
24 to 19,
17 to 11,
9 to 5
80 to 73, Input/
71, output
69 to 63
38 to 35, Output Signals that select division areas 7 to 0 in the
110 to 107
90 Output When this pin is low, it indicates that address output
89 Output When this pin is low, it indicates that the external
88 Output Strobe signal indicating that external address space
87 Output Strobe signal indicating that external address space
132 Input
130 Output External bus request signal when the internal bus
131 Output Indicates the bus is released to the external bus
85 Output Upper column address strobe signal for accessing
86 Output Lower column address strobe signal for accessing
— Output Upper data mask enable signal for 16-bit
— Output Lower-data mask enable signal for accessing the
Function
These pins constitute a bidirectional data bus.
external address space.
on the address bus is valid.
address space is being read.
is to be written, and the upper half (D15 to D8) of the
data bus is enabled.
Write enable signal for accessing the DRAM space.
is to be written, and the lower half (D7 to D0) of the
data bus is enabled.
The external bus master requests the bus to this
LSI.
master accesses the external space in external bus
release state.
master.
the 16-bit DRAM space.
Column address strobe signal for accessing the 8-bit
DRAM space.
the 16-bit DRAM space.
synchronous DRAM for accessing the 16-bit
synchronous DRAM space.
Data mask enable signal for accessing the 8-bit
synchronous DRAM space.
16-bit synchronous DRAM interface space.
Rev. 1.0, 09/01, page 11 of 904