Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 561

Table 11.21 TIORL_0
Bit 3 Bit 2 Bit 1
IOC3 IOC2 IOC1
0 0 0
1
1 0
1
1 0 0
1
1 x
Legend: x: Don't care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Description
Bit 0 TGRC_0
IOC0 Function
0 Output
compare
1
register*
0
1
0
1
0
1
0 Input
capture
register*
1
x
x
TIOCC0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Capture input source is TIOCC0 pin
Input capture at rising edge
Capture input source is TIOCC0 pin
Input capture at falling edge
Capture input source is TIOCC0 pin
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Rev. 1.0, 09/01, page 517 of 904