Refresh Control - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

• RAS Up Mode
To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM
space is interrupted and another space is accessed, the 5$6 signal goes high again. Burst
operation is only performed if DRAM space is continuous. Figure 6.33 shows an example of
the timing in RAS up mode.
ø
Address bus
( )
,
Data bus
Note: n = 2 to 5
Figure 6.33 Example of Operation Timing in RAS Up Mode
6.6.12

Refresh Control

This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing
is used. In addition, self-refreshing can be executed when the chip enters the software standby
state.
Refresh control is enabled when any area is designated as DRAM space in accordance with the
setting of bits RMTS2 to RMTS0 in DRAMCR.
Rev. 1.0, 09/01, page 172 of 904
DRAM space read
T T T
p r c1
Row address Column address 1 Column address 2
(RAST = 0, CAST = 0)
DRAM space
read
T T T
c2 c1 c2
Normal space
read
T T
1 2
External address