Serial Control Register (Scr) - Hitachi H8S/2628 Hardware Manual

14.3.6

Serial Control Register (SCR)

SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also
used to selection of the transfer clock source. For details on interrupt requests, refer to section
14.8, Interrupt Sources. Some bit functions of SCR differ between normal serial communication
interface mode and Smart Card interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit Bit Name
7 TIE
6 RIE
5 TE
4 RE
3 MPIE
2 TEIE
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request
is enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
Transmit Enable
When this bit s set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of
the RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, refer to section 14.5, Multiprocessor
Communication Function.
Transmit End Interrupt Enable
This bit is set to 1, TEI interrupt request is
enabled.
Rev. 1.0, 09/02, page 299 of 568