Mode Register Setting Of Synchronous Dram - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Software
standby
ø
ø
SDRAM
Address bus
Precharge-sel
CKE
DQMU, DQML
Data bus
Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)
Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit
timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the
sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O
port clocks are also stopped.
As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If
synchronous DRAM is connected to the external address space and DRAM data is to be retained
in sleep mode, the ACSE bit must be cleared to 0 in MSTPCR.
Software Standby: When a transition is made to normal software standby, the PALL command is
not output. If synchronous DRAM is connected and DRAM data is to be retained in software
standby, self-refreshing must be set.
6.7.14

Mode Register Setting of Synchronous DRAM

To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to
RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After
that, access the continuous synchronous DRAM space in bytes. When the value to be set in the
synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register
Rev. 1.0, 09/01, page 204 of 904
T T T
Rc2 Rp1 Rp2
NOP
Continuous synchronous DRAM space write
T T T
p r c1
Column address Row address
Row address
PALL ACTV NOP
T T
cl c2
Column address
NOP NOP