Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 18

13.5.3 Timing of Timer Output when Compare-Match Occurs......................................601
13.5.4 Timing of Compare Match Clear .........................................................................602
13.5.5 Timing of TCNT External Reset..........................................................................602
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................603
13.6 Operation with Cascaded Connection ...............................................................................603
13.6.1 16-Bit Counter Mode ...........................................................................................603
13.6.2 Compare Match Count Mode...............................................................................604
13.7 Interrupts ...........................................................................................................................604
13.7.1 Interrupt Sources and DTC Activation.................................................................604
13.7.2 A/D Converter Activation ....................................................................................605
13.8 Usage Notes ......................................................................................................................606
13.8.1 Contention between TCNT Write and Clear........................................................606
13.8.2 Contention between TCNT Write and Increment ................................................606
13.8.3 Contention between TCOR Write and Compare Match ......................................607
13.8.4 Contention between Compare Matches A and B .................................................608
13.8.5 Switching of Internal Clocks and TCNT Operation.............................................609
13.8.6 Mode Setting with Cascaded Connection ............................................................611
13.8.7 Interrupts in Module Stop Mode ..........................................................................611
Section 14 Watchdog Timer ..............................................................................613
14.1 Features .............................................................................................................................613
14.2 Input/Output Pin................................................................................................................614
14.3 Register Descriptions ........................................................................................................614
14.3.1 Timer Counter (TCNT)........................................................................................615
14.3.2 Timer Control/Status Register (TCSR) ................................................................615
14.3.3 Reset Control/Status Register (RSTCSR) ............................................................617
14.4 Operation...........................................................................................................................618
14.4.1 Watchdog Timer Mode ........................................................................................618
14.4.2 Interval Timer Mode ............................................................................................619
14.5 Interrupts ...........................................................................................................................620
14.6 Usage Notes ......................................................................................................................620
14.6.1 Notes on Register Access.....................................................................................620
14.6.2 Contention between Timer Counter (TCNT) Write and Increment .....................621
14.6.3 Changing Value of CKS2 to CKS0......................................................................622
14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................622
14.6.5 Internal Reset in Watchdog Timer Mode.............................................................622
14.6.6 System Reset by WDTOVF Signal......................................................................623
Section 15 Serial Communication Interface (SCI, IrDA)..................................625
15.1 Features .............................................................................................................................625
15.2 Input/Output Pins ..............................................................................................................628
15.3 Register Descriptions ........................................................................................................628
15.3.1 Receive Shift Register (RSR)...............................................................................630
Rev. 1.0, 09/01, page xviii of xliv