Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 9

5.3.7 Software Standby Release IRQ Enable Register (SSIER) ...................................88
5.4 Interrupt Sources ...............................................................................................................88
5.4.1 External Interrupts................................................................................................88
5.4.2 Internal Interrupts.................................................................................................89
5.5 Interrupt Exception Handling Vector Table ......................................................................90
5.6 Interrupt Control Modes and Interrupt Operation .............................................................95
5.6.1 Interrupt Control Mode 0 .....................................................................................95
5.6.2 Interrupt Control Mode 2 .....................................................................................97
5.6.3 Interrupt Exception Handling Sequence ..............................................................98
5.6.4 Interrupt Response Times ....................................................................................100
5.6.5 DTC and DMAC Activation by Interrupt ............................................................101
5.7 Usage Notes ......................................................................................................................102
5.7.1 Contention between Interrupt Generation and Disabling .....................................102
5.7.2 Instructions that Disable Interrupts ......................................................................103
5.7.3 Times when Interrupts are Disabled.....................................................................103
5.7.4 Interrupts during Execution of EEPMOV Instruction..........................................103
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting..............................................103
Section 6 Bus Controller (BSC)........................................................................ 105
6.1 Features .............................................................................................................................105
6.2 Input/Output Pins ..............................................................................................................107
6.3 Register Descriptions ........................................................................................................109
6.3.1 Bus Width Control Register (ABWCR) ...............................................................110
6.3.2 Access State Control Register (ASTCR)..............................................................110
6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL,
WTCRBH, and WTCRBL) ..................................................................................111
6.3.4 Read Strobe Timing Control Register (RDNCR).................................................116
CS Assertion Period Control Registers H, L (CSACRH, CSACRL) ...................117
6.3.5
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1
Burst ROM Interface Control Register (BROMCRL) .........................................119
6.3.7 Bus Control Register (BCR) ................................................................................120
6.3.8 DRAM Control Register (DRAMCR) .................................................................122
6.3.9 DRAM Access Control Register (DRACCR) ......................................................129
6.3.10 Refresh Control Register (REFCR)......................................................................132
6.3.11 Refresh Timer Counter (RTCNT) ........................................................................135
6.3.12 Refresh Time Constant Register (RTCOR)..........................................................135
6.4 Bus Control .......................................................................................................................135
6.4.1 Area Division .......................................................................................................135
6.4.2 Bus Specifications................................................................................................137
6.4.3 Memory Interfaces ...............................................................................................138
6.4.4 Chip Select Signals ..............................................................................................140
6.5 Basic Bus Interface ...........................................................................................................141
6.5.1 Data Size and Data Alignment .............................................................................141
Rev. 1.0, 09/01, page ix of xliv