C Bus Mode Register (Icmr) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Bit Bit Name Initial Value R/W
6 SCP 1
5 SDAO 1

4 1
3 SCLO 1

2 1
1 IICRST 0

0 1
2
16.3.3 I

C Bus Mode Register (ICMR)

ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the transfer bit count.
Description
W Start Condition/Stop Condition Prohibit
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in SCP. A
retransmit start condition is issued in the same way. To
issue a stop condition, write 0 in BBSY and 0 in SCP. This
bit is always read as 1. If 1 is written, the data is not stored.
R/W Monitors the output level of SDA.
0: When reading, SDA pin outputs low.
1: When reading, SDA pin outputs high.
The write value must always be 1.
R/W Reserved
The write value must always be 1.
R This bit monitors SCL output level. When reading and
SCLO is 1, SCL pin outputs high. When reading and SCLO
is 0, SCL pin outputs low.

Reserved
This bit is always read as 1.
R/W IIC control part reset
This bit resets control parts except for I
bit is set to 1 when hang-up is occurred because of
communication failure during I
can be reset without setting ports and initializing registers.

Reserved
This bit is always read as 1.
2
C registers. If this
2 2
C operation, I C control part
Rev. 1.0, 09/01, page 713 of 904