11.10.5 Contention Between Tcnt Write And Increment Operations - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

ø
Address
Write signal
Counter clearing
signal
TCNT
Figure 11.45 Contention between TCNT Write and Clear Operations

11.10.5 Contention between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 11.46 shows the timing in this case.
ø
Address
Write signal
TCNT input
clock
TCNT
Figure 11.46 Contention between TCNT Write and Increment Operations
TCNT write cycle
T1 T2
TCNT address
N H'0000
TCNT write cycle
T1 T2
TCNT address
N M
TCNT write data
Rev. 1.0, 09/01, page 565 of 904