Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 215

 the RCDM bit or BE bit is cleared to 0
If a transition is made to the all-module-clocks-stopped mode in the 5$6 down state, the clock
will stop with 5$6 low. To enter the all-module-clocks-stopped mode with 5$6 high, the
RCDM bit must be cleared to 0 before executing the SLEEP instruction.
T
ø
Address bus Row address
( )
,
Data bus
Note: n = 2 to 5
Figure 6.32 Example of Operation Timing in RAS Down Mode
DRAM space read
T T
p r c1
Column address 1
(RAST = 0, CAST = 0)
Normal space
read
T T T
c2 1 2
External address
Rev. 1.0, 09/01, page 171 of 904
DRAM space
read
T T
c1 c2
Column address 2