Operation Timing; Tcnt Incrementation Timing - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

H'FF
TCORA
TCORB
H'00
TMO
13.5

Operation Timing

13.5.1

TCNT Incrementation Timing

Figure 13.3 shows the count timing for internal clock input. Figure 13.4 shows the count timing
for external clock signal. Note that the external clock pulse width must be at least 1.5 states for
incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The
counter will not increment correctly if the pulse width is less than these values.
ø
Internal clock
Clock input
to TCNT
TCNT
Rev. 1.0, 09/01, page 600 of 904
TCNT
Figure 13.2 Example of Pulse Output
N–1
Figure 13.3 Count Timing for Internal Clock Input
Counter clear
N N+1