Sci Initialization (Clocked Synchronous Mode) - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

15.6.2

SCI Initialization (Clocked Synchronous Mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit
to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of
RDR.
Start of initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
Set data transfer format in
SMR and SCMR
Set value in BRR
1-bit interval elapsed?
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should
both be cleared to 0 or set to 1 simultaneously.
Wait
No
Yes
Figure 15.15 Sample SCI Initialization Flowchart
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
[2] Set the data transfer format in SMR
and SCMR.
[1]
[3] Write a value corresponding to the bit
rate to BRR. (Not necessary if an
external clock is used.)
[2]
[4] Wait at least one bit interval, then set
the TE and RE bits in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
[3]
bits.
Setting the TE and RE bits enable the
TxD and RxD pins to be used.
[4]
Rev. 1.0, 09/01, page 677 of 904