Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 17

11.10.10 Contention between Buffer Register Write and Input Capture ........................568
11.10.11 Contention between Overflow/Underflow and Counter Clearing ....................569
11.10.12 Contention between TCNT Write and Overflow/Underflow ...........................570
11.10.13 Multiplexing of I/O Pins ..................................................................................570
11.10.14 Interrupts and Module Stop Mode ...................................................................570
Section 12 Programmable Pulse Generator (PPG) ........................................... 571
12.1 Features .............................................................................................................................571
12.2 Input/Output Pins ..............................................................................................................573
12.3 Register Descriptions ........................................................................................................573
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL).........................................574
12.3.2 Output Data Registers H, L (PODRH, PODRL) ..................................................575
12.3.3 Next Data Registers H, L (NDRH, NDRL)..........................................................576
12.3.4 PPG Output Control Register (PCR)....................................................................578
12.3.5 PPG Output Mode Register (PMR)......................................................................579
12.4 Operation...........................................................................................................................581
12.4.1 Output Timing......................................................................................................582
12.4.2 Sample Setup Procedure for Normal Pulse Output ..............................................583
12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) ..........584
12.4.4 Non-Overlapping Pulse Output............................................................................585
12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ..............................586
12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase
Complementary Non-Overlapping Output)..........................................................587
12.4.7 Inverted Pulse Output...........................................................................................588
12.4.8 Pulse Output Triggered by Input Capture ............................................................589
12.5 Usage Notes ......................................................................................................................589
12.5.1 Module Stop Mode Setting ..................................................................................589
12.5.2 Operation of Pulse Output Pins............................................................................589
Section 13 8-Bit Timers (TMR)........................................................................ 591
13.1 Features .............................................................................................................................591
13.2 Input/Output Pins ..............................................................................................................593
13.3 Register Descriptions ........................................................................................................593
13.3.1 Timer Counter (TCNT) ........................................................................................593
13.3.2 Time Constant Register A (TCORA)...................................................................594
13.3.3 Time Constant Register B (TCORB) ...................................................................594
13.3.4 Timer Control Register (TCR) ............................................................................594
13.3.5 Timer Control/Status Register (TCSR) ................................................................596
13.4 Operation...........................................................................................................................599
13.4.1 Pulse Output.........................................................................................................599
13.5 Operation Timing ..............................................................................................................600
13.5.1 TCNT Incrementation Timing .............................................................................600
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................601
Rev. 1.0, 09/01, page xvii of xliv