Relation Between Dmac And External Bus Requests, Refresh Cycles, And Exdmac - Hitachi H8S/2378, H8S/2378R Series Hardware Manual

16 bit single-chip microcomputer

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Relation between DMAC and External Bus Requests, Refresh Cycles,

When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle, or

external bus release cycle may arise. In this case, the bus controller will suspend the transfer and

insert a refresh cycle, EXDMAC cycle, or external bus release cycle, in accordance with the

external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An

external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed

until the DMAC releases the external bus.)

When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after

an external write cycle. The external read cycle and external write cycle are inseparable, and so the

bus cannot be released between these two cycles.

When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC

cycle may be executed at the same time as a refresh cycle, EXDMAC cycle, or external bus

release cycle.

Rev. 1.0, 09/01, page 308 of 904

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Figure 7.34 Example of Multi-Channel Transfer

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Channel 1 transfer

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