Hitachi H8S/2378, H8S/2378R Series Hardware Manual page 34

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ........................................674
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ........................................675
Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First) ..............676
Figure 15.15 Sample SCI Initialization Flowchart......................................................................677
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ..................679
Figure 15.17 Sample Serial Transmission Flowchart .................................................................680
Figure 15.18 Example of SCI Operation in Reception ...............................................................681
Figure 15.19 Sample Serial Reception Flowchart.......................................................................682
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations.......684
Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections................................685
Figure 15.22 Normal Smart Card Interface Data Format............................................................686
Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0).......................................................686
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1).....................................................686
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Bit Rate)..............................................................688
Figure 15.26 Retransfer Operation in SCI Transmit Mode.........................................................690
Figure 15.27 TEND Flag Generation Timing in Transmission Operation..................................690
Figure 15.28 Example of Transmission Processing Flow...........................................................691
Figure 15.29 Retransfer Operation in SCI Receive Mode ..........................................................692
Figure 15.30 Example of Reception Processing Flow ................................................................693
Figure 15.31 Timing for Fixing Clock Output Level..................................................................693
Figure 15.32 Clock Halt and Restart Procedure..........................................................................694
Figure 15.33 Block Diagram of IrDA .........................................................................................695
Figure 15.34 IrDA Transmit/Receive Operations .......................................................................696
Figure 15.35 Example of Synchronous Transmission Using DTC .............................................702
Figure 15.36 Sample Flowchart for Mode Transition during Transmission ...............................704
Figure 15.37 Port Pin States during Mode Transition
(Internal Clock, Asynchronous Transmission).......................................................705
Figure 15.38 Port Pin States during Mode Transition
(Internal Clock, Synchronous Transmission).........................................................705
Figure 15.39 Sample Flowchart for Mode Transition during Reception ....................................706
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Section 16 I C Bus Interface2 (IIC2) (Option)
Figure 16.1 Block Diagram of I
Figure 16.2 External Circuit Connections of I/O Pins ................................................................709
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Figure 16.3 I C Bus Formats.......................................................................................................720
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Figure 16.4 I C Bus Timing........................................................................................................720
Figure 16.5 Master Transmit Mode Operation Timing 1............................................................722
Figure 16.6 Master Transmit Mode Operation Timing 2............................................................722
Figure 16.7 Master Receive Mode Operation Timing 1 .............................................................724
Figure 16.8 Master Receive Mode Operation Timing 2 .............................................................724
Figure 16.9 Slave Transmit Mode Operation Timing 1 ..............................................................726
Figure 16.10 Slave Transmit Mode Operation Timing 2 ............................................................727
Figure 16.11 Slave Receive Mode Operation Timing 1..............................................................728
Rev. 1.0, 09/01, page xxxiv of xliv
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C Bus Interface2......................................................................708