Idma1 Mask Register (Idmr1) (Single-Buffer Mode); Burst Timing (Single-Buffer Mode) - Freescale Semiconductor MPC850 User Manual

IDMA Emulation
Bits 0
Field
Reset
R/W
Addr
Figure 19-14. IDMA1 Status Register (IDSR1) (Single-Buffer Mode)

19.3.9.3 IDMA1 Mask Register (IDMR1) (Single-Buffer Mode)

IDMR1 in single-buffer mode behaves the same way as defined above; see
Section 19.3.3.3, "IDMA Mask Registers (IDMR1 and IDMR2)." Figure 19-14 above
shows the mask register's format in single-buffer mode. IDMR1's internal address (IMMR
offset) is 0x914.

19.3.9.4 Burst Timing (Single-Buffer Mode)

A typical single-address burst timing when IDMA1 is in single-buffer mode, is illustrated
in Figure 19-15. The peripheral asserts DREQ0 and waits for SDACK1 to initiate a burst
transfer to memory. The peripheral must negate DREQ0 before the last beat of the transfer;
otherwise, IDMA assumes that another DMA request is pending—DCMR[STR] will not
be cleared—and immediately initiates another transfer. If no buffer is available when this
extra transfer begins, erratic operation occurs.
1 2
—
0000_0000_0000_0000
MPC850 Family User's Manual
3 4
R/W
IMMR + 0x910
5 6
DONE
7
—