Scc Transparent Event Register (Scce)/Mask Register (Sccm) - Freescale Semiconductor MPC850 User Manual

Bit Name
I
3 Interrupt. Note that clearing this bit does not disable SCCE[TXE].
0 No interrupt is generated after this buffer is serviced.
1 When the CPM services this buffer, SCCE[TXB] or SCCE[TXE] is set. These bits can cause
interrupts if they are enabled.
4 L Last in message.
0 The last byte in the buffer is not the last byte in the transmitted transparent frame. Data from the
next transmit buffer is sent immediately after the last byte of this buffer.
1 The last byte in the buffer is the last byte in the transmitted transparent frame. After this buffer is
sent, the transmitter requires synchronization before the next buffer is sent.
TC
5 Transmit CRC.
0 No CRC sequence is sent after this buffer.
1 A frame check sequence defined by GSMR_H[TCRC] is sent after the last byte of this buffer.
CM
6 Continuous mode.
0 Normal operation.
1 The CPM does not clear TxBD[R] after this BD is closed, so the buffer is automatically resent when
the CPM accesses this BD next. However, TxBD[R] is cleared if an error occurs during
transmission, regardless of how CM is set.
7–13 — Reserved, should be cleared.
14 UN Underrun. Set when the SCC encounters a transmitter underrun condition while sending the buffer.
15 CT CTS lost. Indicates the CTS was lost during frame transmission.
Data length and buffer pointer fields are described in Section 21.3, "SCC Buffer
Descriptors (BDs)." Although it is never modified by the CP, data length should be greater
than zero. The buffer pointer can be even or odd and can reside in internal or external
memory.
28.12 SCC Transparent Event Register (SCCE)/Mask
Register (SCCM)
When the SCC is in transparent mode, the SCC event register (SCCE) functions as the
transparent event register to report events recognized by the transparent channel and to
generate interrupts. When an event is recognized, the transparent controller sets the
corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing, the
equivalent bits in the transparent mask register (SCCM).
Event bits are reset by writing ones; writing zeros has no effect. All unmasked bits must be
reset before the CPM negates the internal interrupt request signal. Figure 28-4 shows the
event and mask registers.

SCC Transparent Event Register (SCCE)/Mask Register (SCCM)

Table 28-8. SCC Transparent Tx BD Status
and Control Field Descriptions (Continued)
Chapter 28. SCC Transparent Mode
Description