Scc Bisync Parameter Ram - Freescale Semiconductor MPC850 User Manual

SCC BISYNC Parameter RAM

26.4 SCC BISYNC Parameter RAM
When BISYNC mode is selected in GSMR_L[MODE], the protocol-specific area of the
SCC parameter RAM is mapped as in Table 26-1.
Table 26-1. SCC BISYNC Parameter RAM Memory Map
1
Offset Name
0x30 —
CRCC
0x34
PRCRC
0x38
PTCRC
0x3A
PAREC
0x3C
BSYNC
0x3E
BDLE
0x40
0x42 CHARACTER1 Hword Control character 1–8. These values represent control characters that the
CHARACTER2 Hword
0x44
CHARACTER3 Hword
0x46
CHARACTER4 Hword
0x48
CHARACTER5 Hword
0x4A
CHARACTER6 Hword
0x4C
CHARACTER7 Hword
0x4E
0x50 CHARACTER8 Hword
RCCM
0x52
1
From SCC base. SCC base = IMMR + 0x3D00 (SCC2) or 0x3E00 (SCC3)
The SYN1–SYN2 synchronization characters are programmed in the DSR (see
Section 21.2.3, "Data Synchronization Register (DSR).") The BISYNC controller uses the
same basic data structure as other modes; receive and transmit errors are reported through
their respective BDs. Line status is reflected on port C pins and a maskable interrupt is
generated when the status changes. There are two basic ways to handle BISYNC channels:
• The controller can inspect data on a per-byte basis and interrupt the core each time
a byte is received.
• The controller can be programmed so software handles the first two or three bytes.
The controller directly handles subsequent data without interrupting the core.
Width
Word Reserved
Word CRC constant temporary value.
Hword Preset receiver/transmitter CRC16/LRC. These values should be preset to all
ones or zeros, depending on the BCS used.
Hword
Hword Receive parity error counter. This 16-bit (modulo 2
CP counts parity errors on receive if the parity feature of BISYNC is enabled.
Initialize PAREC while the channel is disabled.
Hword BISYNC SYNC register. Contains the value of the SYNC to be sent as the
second byte of a DLE–SYNC pair in an underrun condition and stripped from
incoming data on receive once the receiver synchronizes to the data using the
DSR and SYN1–SYN2 pair. See Section 26.7, "BISYNC SYNC Register
(BSYNC)."
Hword BISYNC DLE register. Contains the value to be sent as the first byte of a
DLE–SYNC pair and stripped on receive. See Section 26.8, "SCC BISYNC DLE
Register (BDLE)."
BISYNC controller recognizes. See Section 26.6, "SCC BISYNC Control
Character Recognition."
Hword Receive control character mask. Masks CHARACTERn comparison so control
character classes can be defined. Setting a bit enables and clearing a bit masks
comparison. See Section 26.6, "SCC BISYNC Control Character Recognition."
MPC850 Family User's Manual
Description
16
) counter maintained by the