System Protection Control Register (Sypcr) - Freescale Semiconductor MPC850 User Manual

Programming the SIU
Table 10-3. SIUMCR Field Descriptions (Continued)
Bits Name
27 B3DD Bank 3 double drive. If this bit is set, CS3 is reflected on GPL_x3.
28–31 — Reserved, should be cleared.

10.4.3 System Protection Control Register (SYPCR)

The system protection control register (SYPCR) controls the system monitors and bus
monitor timing. It can be read at any time, but can be written only once after system reset.
Bit 0 1
Field
Reset
R/W
SPR
Bit 16 17 18
Field
Reset
R/W
SPR
Figure 10-4. System Protection Control Register (SYPCR)
Table 10-4 describes SYPCR fields.
Bits Name
0–15 SWTC Software watchdog timer count. Count value for the software watchdog timer.
16–23 BMT Bus monitor timing. Defines the timeout period, in 8 system clock resolution, for the bus monitor.
maximum timeout is 2,040 clocks.
24 BME Bus monitor enable. Controls bus monitor operation during internal-to-external bus cycles.
0 Disable the bus monitor.
1 Enable the bus monitor.
Note: If the bus monitor is disabled, transfer error conditions do not cause TEA to be asserted.
25–27 — Reserved, should be cleared.
28 SWF Software watchdog freeze
0 The software watchdog timer continues counting even if FRZ is asserted.
1 The software watchdog timer stops counting when FRZ is asserted.
29 SWE Software watchdog enable.
To disable the software watchdog timer, it should be cleared by the software after a system
reset.
0 Software watchdog timer disabled.
1 Software watchdog timer enabled. (default)
2 3 4 5 6
1111_1111_1111_1111
(IMMR & 0xFFFF0000) + 0x004
19 20 21 22
BMT
1111_1111
(IMMR & 0xFFFF0000) + 0x006
Table 10-4. SYPCR Field Descriptions
MPC850 Family User's Manual
Description
7 8 9 10
SWTC
R/W
23 24 25 26
BME —
0 000
R/W
Description
11 12 13 14
27 28 29 30
SWF SWE SWRI SWP
0 1 1
15
31
1