Chip-Select Signals (Cstx) - Freescale Semiconductor MPC850 User Manual

Table 15-14. RAM Word Bit Settings (Continued)
Bit Name
29 UTA UPM transfer acknowledge. Controls the state of TA sampled by the external bus interface in the
current memory cycle. TA is output at the rising edge of GCLK2_50.
0 TA is driven low on the rising edge of GCLK2_50. The bus master samples it low in the next clock
cycle.
1 TA is driven high on the rising edge of GCLK2_50.
30 TODT Turn-on disable timer. Controls the disable timer mechanism. This bit has meaning only in RAM
words for which UTA = 0; otherwise it is a don't care.
0 The disable timer is turned off.
1 The disable timer for the current bank is activated preventing a new access to the same bank
(when controlled by the UPMs) until the disable timer expires. For example, precharge time.
31 LAST Last. If this bit is set, it is the last RAM word in the program.
0 The UPM continues executing RAM words.
1 The service to the UPM request is done.

15.6.4.2 Chip-Select Signals (CSTx)

If BRx[MS] of the accessed bank selects a UPM on the currently requested cycle the UPM
manipulates the CS signal for that bank with timing as specified in the UPM RAM word.
The selected UPM affects only assertion and negation of the appropriate CSx signal. The
state of the selected CSx signal of the corresponding bank depends on the value of each
CSTn bit.
Figure 15-40 and the timing diagrams in Figure 15-36 and Figure 15-37 shows how UPMs
control CS signals.
UPMA
UPMB
GPCM
Bank Selected
MS[0–1] in BRx
MUX
MS[0–1] Machine
00 GPCM
01 –
10 UPMA
11 UPMB
Figure 15-40. CSx Signal Selection
Chapter 15. Memory Controller
User-Programmable Machines (UPMs)
Description
Switch CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7