Timebase Register (Tbu And Tbl) - Freescale Semiconductor MPC850 User Manual

10.9.1 Timebase Register (TBU and TBL)

The timebase register (TB) holds a 64-bit integer that is incremented periodically. It is
implemented in two parts, time base upper and time base lower (TBU and TBL). There is
no automatic initialization of TB, therefore, system software must perform this
initialization. The contents of TB can be written by mtspr and read by mftb or mftbu
instruction. Figure 10-19 shows TBU. Note that the TBU and TBL are keyed registers.
They must be unlocked in TBK before they can be written.
Bit 0 1 2
Field
Reset
R/W
SPR
Table 10-16 describes TBU fields.
Bits Name
0–31 TBU Timebase upper. The value in this field is used as an upper part of the timebase counter.
Figure 10-20 shows TBL.
Bit 0 1 2
Field
Reset
R/W
SPR
Table 10-17 describes TBL fields.
Bits Name
0–31 TBL Timebase lower. The value in this field is used as the lower part of the timebase register.
3 4 5
269 (Read)/285 (Write)
Figure 10-19. Timebase Upper Register (TBU)
Table 10-16. TBU Field Descriptions
3 4 5
268 (Read)/284 (Write)
Figure 10-20. Timebase Lower Register (TBL)
Table 10-17. TBL Field Descriptions
Chapter 10. System Interface Unit
6 7 8 9
TBU
—
R/W
Description
6 7 8 9
TBL
—
R/W
Description
The PowerPC Timebase
... 30 31
... 30 31