Chip-Select Assertion Timing - Freescale Semiconductor MPC850 User Manual

General-Purpose Chip-Select Machine (GPCM)
Table 15-11. GPCM Strobe Signal Behavior (Continued)
Configuration
ORx SCCR
Access
[TRLX] [EBDF]
1 Read x
Write
00
01
1
SCY is the number of wait cycles from the option register.

15.5.1.1 Chip-Select Assertion Timing

The banks selected by the GPCM support an option to output CS at different timings with
respect to the external address bus. Depending on the value of the ACS field (plus an
additional cycle if TRLX = 1), CS can be output as follows
• Simultaneous with the external address
• One quarter of a clock cycle later
• One half of a clock cycle later
Figure 15-16 shows a basic connection between the MPC850 and an external peripheral
device. Here, CS (the strobe output for the memory access) is connected directly to CE of
the memory device and R/W is connected to the respective R/W in the peripheral device.
Address
ORx ORx
to CS
[CSNT] [ACS]
Asserted
x 00 0
10 1+1/4*Clk
11 1+1/2*Clk
0 00 0
10 1+1/4*Clk
11 1+1/2*Clk
1 00 0
10 1+1/4*Clk
11 1+1/2*Clk
00 0
10 1+1/4*Clk
11 1+1/2*Clk
MPC850 Family User's Manual
Signal Behavior
Address Address Data to
to OE to WE
Asserted Asserted Asserted
3/4*Clk x
1+3/4*Cl
k
x 3/4*Clk -1/4*Clk
1+3/4*Cl 3/4*Clk
k
3/4*Clk -1/4*Clk
1+3/4*Cl 3/4*Clk
k
3/4*Clk -1/4*Clk
1+3/4*Cl 3/4*Clk
k
CS WE
Negated Negated
to to
WE
Address/ Address
Data /Data
Invalid Invalid
x 1/4*Clk x
1/4*Clk
1+1/2*Cl
k
1+1/2*Clk
1/4*Clk 1+3/8*Cl
k
1+3/8*Clk
Total
Cycles
2+2*SCY
3+2*SCY
2+2*SCY
3+2*SCY
4+2*SCY
3+2*SCY
4+2*SCY