Integer Load And Store String Instructions; Branch And Flow Control Instructions - Freescale Semiconductor MPC850 User Manual

Instruction Set Summary
Manual for more information. Table 5-10 lists the integer load and store multiple
instructions for the MPC850.
Table 5-10. Integer Load and Store Multiple Instructions
Load Multiple Word
Store Multiple Word

5.2.4.2.6 Integer Load and Store String Instructions

The integer load and store string instructions allow movement of data from memory to
registers or from registers to memory without concern for alignment. These instructions can
be used for a short move between arbitrary memory locations or to initiate a long move
between misaligned memory fields.
When the MPC850 is operating with little-endian byte order, execution of a load or store
string instruction causes the system alignment error handler to be invoked; see "Byte
Ordering" in Chapter 3, "Operand Conventions," in The Programming Environments
Manual for more information. Table 5-11 lists the integer load and store string instructions.
Table 5-11. Integer Load and Store String Instructions
Load String Word Immediate
Load String Word Indexed
Store String Word Immediate
Store String Word Indexed
Load string and store string instructions may involve operands that are not word-aligned.
As described in "Alignment Exception (0x00600)" in Chapter 6, "Exceptions," in The
Programming Environments Manual, a misaligned string operation suffers a performance
penalty compared to a word-aligned operation of the same type.
When a string operation crosses a page boundary, the instruction may be interrupted by a
DSI exception associated with the address translation of the second page. In this case, the
MPC850 performs some or all memory references from the first page and none from the
second before taking the exception. On return from the DSI exception, the load or store
string instruction will re-execute from the beginning. For more information, refer to "DSI
Exception (0x00300)" in Chapter 6, "Exceptions," in The Programming Environments
Manual.

5.2.4.3 Branch and Flow Control Instructions

Branch instructions are executed by the branch processing unit (BPU). The BPU receives
branch instructions from the fetch unit and performs condition register (CR) lookahead
operations on conditional branches to resolve them early, achieving the effect of a
zero-cycle branch in many cases.
Name
Name
MPC850 Family User's Manual
Mnemonic
lmw rD,d(rA)
stmw rS,d(rA)
Mnemonic
lswi rD,rA,NB
lswx rD,rA,rB
stswi rS,rA,NB
stswx rS,rA,rB
Syntax
Syntax