Interrupt Structure - Freescale Semiconductor MPC850 User Manual

System Configuration
Each register in the keep-alive power region has a key register that can be in an open or
locked state. At power-on reset, all key registers are open, except for the real-time clock key
registers. Each key register has an associated address in the internal memory map, as shown
in Table 10-6. A write of 0x55CC_AA33 to a key register unlocks its associated SIU
register; any other access (including reads or writes of any other value) to a key register
locks its associated SIU register. For example, writing a 0x55CC_AA33 to the RTCK key
register allows the RTC register to be written. The key registers are write-only; a read of the
key register does not return the last value written.
When a register is locked, an attempt to write to it will result in a machine check exception,
and will not change the value in the register. One exception to this is the timebase register
(TBU and TBL), locked with TBK. A write to the timebase register when it is locked results
in a software emulation exception.
Reads are allowed at all times to any of the SIU registers, regardless of whether they are
locked or unlocked.
Write any other value to the key register
Power-on reset
Open Locked
Write 0x55CC_AA33 to the key register
Figure 10-6. Register Lock Mechanism
For more information on key registers, see Section 14.5.7.3, "Register Lock Mechanism:
Protecting SIU Registers in Power-Down Mode."
10.5 System Configuration
The SIU module configuration register (SIUMCR) is used for configuring external bus
arbitration logic, external master support, and pin multiplexing. See Section 10.4.2, "SIU
Module Configuration Register (SIUMCR)."

10.5.1 Interrupt Structure

The SIU receives interrupts from internal sources, like the PIT, real-time clock,
communications processor module (CPM), and the external IRQ pins. Figure 10-7 shows
the MPC850 interrupt structure.
Chapter 10. System Interface Unit