Smc Buffer Descriptors (Bds) - Freescale Semiconductor MPC850 User Manual

Table 30-1. SMCMR Field Descriptions (Continued)
Bits Name
10–11 SM SMC mode.
00 GCI or SCIT support.
01 Reserved.
10 UART (must be selected for SMC UART operation).
11 Totally transparent operation.
12–13 DM Diagnostic mode.
00 Normal operation.
01 Local loopback mode.
10 Echo mode.
11 Reserved.
14 TEN SMC transmit enable.
0 SMC transmitter disabled.
1 SMC transmitter enabled.
15 REN SMC receive enable.
0 SMC receiver disabled.
1 SMC receiver enabled.

30.2.2 SMC Buffer Descriptors (BDs)

In UART and transparent modes, the SMC's memory structure is like the SCC's in that
SMC-associated data is stored in buffers. Each buffer is referenced by a BD and organized
in a BD table located in the dual-port RAM. See Figure 30-3.
Dual-Port RAM
SMC TxBD
SMC RxBD
Pointer to SMCx
RxBD Table
Pointer to SMCx
TxBD Table
Table
Table
Figure 30-3. SMC Memory Structure
Chapter 30. Serial Management Controllers (SMCs)
Common SMC Settings and Configurations
Description
TxBD Table
Status and Control
Data Length
Buffer Pointer
RxBD Table
Status and Control
Data Length
Buffer Pointer
External Memory
Tx Data Buffer
Rx Data Buffer