Immu Real Page Number Register (Mi_Rpn) - Freescale Semiconductor MPC850 User Manual

Programming Model
Table 8-11. MD_TWC Field Descriptions (Continued) (Continued)
Name
Bits
Write Read
30 WT —
31 V —

8.8.6 IMMU Real Page Number Register (MI_RPN)

The IMMU real page number register (MI_RPN), shown in Figure 8-11, contains the
physical address and the memory attributes of an entry to be loaded into a TLB. MI_RPN
should be written after MI_EPN and MI_TWC are written.
Bit 0 1
Field
Reset
R/W
Bit 16 17
Field RPN
Reset
R/W
SPR
Figure 8-11. IMMU Real Page Number Register (MI_RPN)
Write
Writethrough attribute for page entry:
0 Copyback data cache policy. Cleared on DTLB miss.
1 Writethrough data cache policy
0 Entry is not valid
1 Entry is valid. (set on a DTLB miss)
2 3 4 5
18 19 20 21
MPC850 Family User's Manual
Description
6 7 8 9
RPN
—
R/W
22 23 24 25
PP
—
R/W
790
Read
Returns 0 on read.
Returns 0 on read.
10 11 12 13
26 27 28 29
SPS SH
14 15
30 31
CI V