Spll Output Characteristics And Stability; The System Phase-Locked Loop Pins (Vddsyn, Vsssyn Vsssyn1, Xfc) - Freescale Semiconductor MPC850 User Manual

Note that under no condition should the voltage on MODCK1 and MODCK2 exceed the
power supply voltage VDDH applied to the part.
At power-on reset, before the PLL achieves lock, no internal or external clocks are
generated by the MPC850, which may cause higher than normal static current during the
short period of stabilization.

14.2.2.2 SPLL Output Characteristics and Stability

The minimum frequency at which the SPLL is guaranteed to operate is 15 MHz; therefore,
the MPC850 must be configured so that at all times (both after initial system reset and at
the final operating frequency) the minimum frequency of CLKOUT is 15 MHz. The
maximum frequency at which the SPLL is guaranteed to operate is the maximum rated
frequency of the part (for example, 50 MHz for a 50-MHz part).
The multiplication factor is the most important parameter in defining the SPLL stability.
There are three factors related to the multiplication factor that define SPLL stability:
• Phase skew—The time difference between the rising edges of EXTCLK and
CLKOUT for a capacitive load on the CLKOUT pin over the entire process,
temperature ranges, and voltage ranges. For input frequencies greater than 15 MHz
and (MF+1)≤2, this skew is ±0.9 ns. Otherwise, this skew is not guaranteed.
However, for (MF+1)<10 and input frequencies greater than 10 MHz, the skew is
±2.3 ns.
• Phase jitter—A variation in the skew that occurs between the rising edges of
EXCLK and CLKOUT for a specific temperature, voltage, input frequency, MF, and
capacitive load on the CLKOUT pin. These variations are a result of the PLL locking
mechanism. For input frequencies greater than 15 MHz and (MF+1)≤2, this jitter is
less than ±0.6ns. Otherwise, this jitter is not guaranteed. However, for (MF+1)<10
and input frequencies greater than 10 MHz, this jitter is less than ±2ns.
• Frequency jitter—The frequency variation of CLKOUT. For small multiplication
factors, that is, (MF+1)<10, this jitter is smaller than 0.5%. For mid-range
multiplication factors (10<(MF+1)<500), this jitter is between 0.5% and ~2%. For
large multiplication factors ((MF+1)>500), the frequency jitter is 2–3%. The
maximum input frequency jitter on EXTAL is 0.5%. If the rate of change of the
frequency of EXTAL is slow (that is, it does not jump between the minimum and
maximum values in one cycle), the maximum jitter can be 2%.
14.2.2.3 The System Phase-Locked Loop Pins (VDDSYN, VSSSYN,
VSSSYN1, XFC)
The internal frequency of the MPC850 and the output of the CLKOUT pin depend on the
quality of the input clock source and the PLPRCR[MF]. The SPLL contains the following
dedicated pins that are isolated from common power and ground.
Chapter 14. Clocks and Power Control
The Clock Module