Memory Attributes - Freescale Semiconductor MPC850 User Manual

Memory Attributes

In this mode, the MMU page tables defined for the software tablewalk resolve to a
single level-two descriptor entry for a 1-Kbyte page. This is done by allowing
manipulation of the subpage validity flags of a 4-Kbyte page. For example:
— To define a 4-Kbyte page with uniform protection, create four level-two
descriptors for the 4-Kbyte page, each with subpage validity flags set to 0b1111.
All other fields of the level-two descriptors must also be the same for each of
these entries.
— To define four different 1-Kbyte pages, create four level-two descriptors, but set
the subpage validity flags such that: entry one = 0b1000, entry two = 0b0100,
entry three = 0b0010, entry four = 0b0001. All other fields of the level-two
descriptor can be set differently for each of these entries.
— To define two different 2-Kbyte pages, create four level-two descriptors, but set
the subpage validity flags in pairs such that: entry one = 0b1100, entry two =
0b1100, entry three = 0b0011, entry four = 0b0011. The other fields of the
'paired' level-two descriptors must be the same for each of the pairs.
Other combinations are also possible.
This mode is the most complex and the most inefficient in memory size (that is,
MMU tables are approximately four times larger). However, it allows the most
detailed resolution of protection with full functionality.
IMMUs and DMMUs can use different modes; the IMMU could use mode 1 and the
DMMU could use mode 2, or vice versa. However, if mode 3 is desired, both MMUs must
be in mode 3.
8.6 Memory Attributes
Memory attributes defined by the PowerPC architecture are implemented as follows:
• Reference and change bit updates—The MPC850 does not generate an exception for
an R (reference) bit update. In fact, there is no entry for an R bit in the TLB.
The change bit (C) is bit 23 in the level-two descriptor, described in Table 8-4.
Software updates C (changed) bits, but hardware treats the C bit (negated) as a
write-protect attribute. Therefore, attempting to write to a page marked unmodified
invalidates that entry and causes an implementation-specific DTLB error exception.
If change bits are not needed, set the C bit to one by default in the PTEs.
• Memory control attributes—The MPC850 supports cache inhibit (CI), writethrough
(WT), and guarded (G) attributes, defined in the PowerPC Virtual Environment
Architecture (VEA). The memory coherence (M) attribute is not supported; to
ensure memory coherency, configure the page as cache-inhibited. Chapter 7,
"Instruction and Data Caches," describes the effects of CI and WT attributes in the
MPC850.
MPC850 Family User's Manual