Program Exception (0X00700) - Freescale Semiconductor MPC850 User Manual

6.1.2.7 Program Exception (0x00700)

A program exception occurs when no higher priority exception exists and one or more of
the following exception conditions, which correspond to bit settings in SRR1, occur during
execution of an instruction:
• An lswx instruction for which rA or rB is in the range of registers to be loaded (may
cause results that are boundedly undefined)
• Privileged instruction—A privileged instruction type program exception is
generated when the execution of a privileged instruction is attempted and the
processor is operating in user mode (MSR[PR] is set). It is also generated for mtspr
or mfspr instructions that have an invalid SPR field that contain one of the defined
values having spr[0] = 1 and if MSR[PR] = 1. Some implementations may also
generate a privileged instruction program exception if a specified SPR field (for a
move to/from SPR instruction) is not defined for a particular implementation, but
spr[0] = 1; in this case, the implementation may cause either a privileged instruction
program exception, or an illegal instruction program exception may occur instead.
• Trap—A trap program exception is generated when any of the conditions specified
in a trap instruction is met. Trap instructions are described in Section 5.2.4.4, "Trap
Instructions."
The register settings when a program exception is taken are shown in Table 6-8.
Table 6-8. Register Settings after a Program Exception
Register
SRR0 • Set to the EA of the instruction that causes the exception.
SRR1 0
1–4
5–9
10
Note that only one of bits 11–14 of SRR1 can be set at a time.
11
12
13
14
15
16–31
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR POW 0
ILE —
EE 0
PR 0
When a program exception is taken, instruction execution resumes at offset 0x00700 from
the physical base address indicated by MSR[IP].
Setting Description
Loaded with equivalent bits from the MSR
Cleared
Loaded with equivalent bits from the MSR
Cleared
Cleared.
Set for an illegal instruction program exception; otherwise cleared.
Set for a privileged instruction program exception; otherwise cleared.
Set for a trap program exception; otherwise cleared.
Cleared if SRR0 contains the address of the instruction causing the exception, and set
if SRR0 contains the address of a subsequent instruction.
Loaded with equivalent bits from the MSR
FP 0
ME —
SE 0
BE 0
Chapter 6. Exceptions
IP — LE
IR 0
DR 0
RI 0
Exceptions
Set to value of ILE