Retry - Freescale Semiconductor MPC850 User Manual

Bus Operations
To properly control termination of a bus cycle for a bus error, TEA must be asserted at the
same time or before TA is asserted. Once TEA is sampled as asserted, it should be negated
before the next rising edge to avoid influencing the next initiated bus cycle. TEA is an
open-drain pin that allows the wire-OR of different sources of error generation.

13.4.10.1 RETRY

When an external device asserts RETRY during a bus cycle, the MPC850 enters a sequence
in which it terminates the current transaction, relinquishes bus ownership, and retries the
cycle using the same address, address attributes, and data (in the case of a write cycle).
Figure 13-28 shows that when the internal arbiter is enableMPC850d, MPC850 negates BB
and asserts BG in the clock cycle after RETRY is detected to allow any external master to
gain bus ownership. Normal arbitration resumes in the next clock cycle. If the external
master does not use the bus, the MPC850 initiates a new transfer with the same address and
attributes as before. In Figure 13-29 the same situation is shown where the MPC850 is
working with an external arbiter. In this case, in the clock cycle after RETRY is detected
asserted, BR and BB are negated together. Normal arbitration resumes one clock cycle later.
CLKOUT
BR
BG (Output)
BB
A[6–31]
R/W
TSIZ[0–1]
BURST
TS
Data
TA
RETRY
Figure 13-28. Retry Transfer Timing–Internal Arbiter
Allow external master
to gain the bus
A
MPC850 Family User's Manual
A