Highest Priority Interrupt; Nested Interrupts; Masking Interrupt Sources In The Cpm - Freescale Semiconductor MPC850 User Manual

Masking Interrupt Sources in the CPM

USB and SCC entries can be grouped or spread by clearing or setting CICR[SPS],
respectively; SPS cannot be changed dynamically. These options are described as follows:
• If SPS = 1, the USB and 2 SCCs are grouped at the top of the priority table, ahead
of most other CPM interrupt sources. Grouping is useful where USB and 2 SCCs
function at a very high data rate and interrupt latency is critical.
• If SPS = 0, the USB and 2 SCC priorities are spread over the table so other sources
can have lower interrupt latencies than the USB and SCCs.

35.2.2 Highest Priority Interrupt

The highest priority interrupt source can be selected dynamically by entering the interrupt
number in CICR[HPn], described in Table 35-3. This interrupt is still within the same
interrupt level specified in CICR[IRL] but is serviced before any other CPM interrupt (that
is, if this type of interrupt is pending, its vector number returns first when the CIVR is read.

35.2.3 Nested Interrupts

The CPIC supports a fully nested interrupt environment that allows a high priority interrupt
from another CPM source to suspend a lower priority service routine. An interrupt request
with highest priority is presented to the core for servicing, which the core acknowledges by
setting CIVR[IACK]. After IACK is set, the corresponding vector is indicated in the CIVR
and the request is cleared. The next request can be presented to the core. When the interrupt
is taken, the external interrupt enable bit of the core's machine state register, MSR[EE] is
cleared to disable further interrupt requests until software can handle them.
The CPM interrupt in-service register (CISR) can be used to allow a higher priority
interrupt within the same interrupt level to be presented to the core before a lower priority
interrupt service completes. Each CISR bit corresponds to a CPM interrupt source. When
the core acknowledges the interrupt by setting IACK, the CPIC sets the CISR bit for that
interrupt source. This prevents subsequent CPM interrupt requests at this priority level or
lower, until the current interrupt is serviced and the CISR bit is cleared. Lower-priority
interrupts can still be set in the CPIC during this time, but they will pend until the CISR bit
for the higher-priority interrupt is cleared. Therefore, in the interrupt service routine for the
CPM interrupts, the core external interrupt enable MSR[EE] can be set to allow
higher-priority interrupts within the CPM or from other sources to generate an interrupt
request.
35.3 Masking Interrupt Sources in the CPM
An interrupt is masked by clearing and enabled by setting the corresponding CIMR bit; see
Section 35.5.3, "CPM Interrupt Mask Register." When a masked source requests an
interrupt, the corresponding CIPR bit is set but the CPIC does not signal the interrupt to the
core. Masking all sources allows the implementation of a polling interrupt servicing
scheme.
MPC850 Family User's Manual