Communicating With The Core; Communicating With The Peripherals - Freescale Semiconductor MPC850 User Manual

Communicating with the Core

Figure 18-1 is a block diagram of the CP.
INSTRUCTION STORAGE
RAM
ROM
Sequencer
Scheduler
Service Requests
Figure 18-1. Communications Processor (CP) Block Diagram
18.2 Communicating with the Core
The CP communicates with the core in the following ways:
• By exchanging parameters using the dual-port RAM.
• By executing special commands that are issued by the core through the CP
command register (CPCR).
• By generating interrupts using the CPM interrupt controller (CPIC).
• By letting the core read the CPM status/event registers at any time.

18.3 Communicating with the Peripherals

The CP uses the peripheral bus to communicate with the peripherals. The serial
communications controller (SCCs) and the universal serial bus (USB) have separate receive
and transmit FIFOs. The SCC2 receive and transmit FIFOs are 32 bytes each; the USB and
SCC3 FIFOs are 16 bytes each. The serial management controllers (SMCs), serial
peripheral interface (SPI), and I
two characters.
Decoder
Register
File
•
Development
•
Support
•
2
C are all double-buffered, creating effective FIFO sizes of
MPC850 Family User's Manual
PROCESSING UNITS
Multiplier/
Accumulator
Cyclic
Redundancy
DMA
Check
Arithmetic
Logic Unit
Dual-Port
RAM
Peripheral
Interface
Peripheral
Bus