Exceptions
6.1.6 Exception Latency
Figure 6-1 describes significant events during exception processing.
3
1
2
0
A
B
•••
1
2
3
4
5
6
7
Stage
Fetch (in IQ)
In dispatch entry (IQ0)
Execute
Complete (In CQ)
In retirement entry (CQ0)
Instruction Queue
6
7
5
6
4
5
3
4
Completion Queue
2
3
1
2
3
4
5
6
7
8
C
IH1
IH2
IH2
IH1
Figure 6-1. Exception Latency
MPC850 Family User's Manual
9
10
11
12
13
D
IH3
IH4
IH4
IH4
IH4
IH4
IH4
IH3
IH3
IH3
IH3
IH3
IH2
IH2
IH2
IH2
IH2
IH1
IH1
IH1
IH1
IH1
14
15
16
17
18
E
IH5
IH6
IH5
IH6
IH7
IH8
IH4
IH5
IH6
IH7
IH3
IH4
IH5
IH6
IH2
IH3
IH4
IH5
IH2
IH3
IH4
IH1
IH1
IH2
IH3