Utopia Single-Phy - Freescale Semiconductor MPC850 User Manual

Mpc850 family integrated communications microprocessor
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43.2 UTOPIA Single-PHY

The MPC850SR acts as an ATM layer UTOPIA master per the ATM Forum UTOPIA level 1
specification for an ATM single-PHY configuration. The MPC850SR implements the
UTOPIA interface as an 8-bit wide bidirectional data bus using a cell-level handshake, and
operates at frequencies up to 25 MHz. The UTOPIA controller controls all interface signals.
Assertion of transmit cell available (TxCav) or receive cell available (RxCav) issues a request
to the CP to handle a receive or transmit operation. During the cell transfer, the UTOPIA
controller controls the enable signals (TxEnb or RxEnb) and the transmit start of cell signal
(TxSOC). It also samples the RxSOC signal during the cell transfer.
Most of the UTOPIA signals are multiplexed on MPC850SR port D pins as shown in Figure
43-1. The IDMA request connected to the DREQ0 signal is replaced with RxClav. TxClav
signal is connected to the port C[12] signal.
The MPC850SR implements a cell level interface. The cell level handshake is identical to the
octet level handshake except that once the TxClav or RxClav signals are asserted the PHY
must be capable of receiving or transmitting a whole cell. The MPC850SR transmits or
receives a whole cell directly to or from system memory during a receive or transmit
operation.
PHY
TxEnb
TxClav
Tx
TxSOC
TxData
TxClk
RxClk
RxData
Rx
RxSOC
RxClav
RxEnb
Figure 43-1. MPC850SR UTOPIA Interface
Chapter 43. UTOPIA Interface
MPC850SR
PD10
PC12
Up to 25 MHz
UTPClk(PD)
UTPB(PD12–15; 4–7)
SOC(PD3)
DREQ0(PC15)
PD11
UTOPIA Single-PHY

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